View TP6508_202177.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TOPRO
TP6508
Advanced Panel-2 Video Graphic Array
Specification
Version: 2.02 Revision: 2.01a 1999/04/12
Topro Technology Incorporation
Revision History
Revision
2.02
Date .
88.04.12
Comment
Change for Topro version .
.
ii
TP6508 Target Spec. List
Revision History ...............................................................................................................ii I. General Description .................................................................................................... 1 II. Feature ....................................................................................................................... 3 III. Pin Configurations ................................................................................................... 5
ISA Bus Interface Connections ............................................................................................................. 5 PCI Local Bus Interface Connections ................................................................................................... 6
IV. Functional Block Diagram ....................................................................................... 7
System Block Diagram ......................................................................................................................... 7 VGA Block Diagram ............................................................................................................................ 8 True-Color Palette DAC Block Diagram .............................................................................................. 9 Dual Frequency Synthesizer Block Diagram ....................................................................................... 10 Panel Controller Block Diagram ........................................................................................................ 11 Graphics Engine Diagram ................................................................................................................... 12 Memory Configuration Block Diagram ..................................................................... 13
V. Pin Descriptions ........................................................................................................ 15 VI. Function Descriptions ............................................................................................ 26
Host Bus Interface .............................................................................................................................. 26 Sequencer Controller (SEQC) ............................................................................................................ 26 CRT Controller (CRTC) ..................................................................................................................... 26 Attribute Controller (ATC) ................................................................................................................. 27 Graphics Controller (GFXC) .............................................................................................................. 27 Address Multiplexer (AMUX) ........................................................................................................... 27 CRT FIFO (Display FIFO) ................................................................................................................. 28 Attribute FIFO .................................................................................................................................... 28 Write Buffer ........................................................................................................................................ 28 Dual Frequency Synthesizer ................................................................................................................ 28 True-Color Palette DAC (TDAC) ...................................................................................................... 29 Graphics Engine Controller (GEC) .................................................................................................... 29 Command FIFO .................................................................................................................................. 32 Hardware Cursor Controller .............................................................................................................. 32 PC Video Controller ........................................................................................................................... 33 LCD Line Buffer ................................................................................................................................. 33 Panel Controller ................................................................................................................................. 34 Power Management Controller (P.M.C.) ............................................................................................ 39
VII. Registers ................................................................................................................ 42
IBM Standard Register ....................................................................................................................... 42 Backward Compatible Register Description ...................................................................................... 48 Extended Sequencer Register Description .......................................................................................... 51 Extended CRTC Register Description ................................................................................................ 64 Panel Control Register Description .................................................................................................... 67 PCI Local Bus Configuration Register Description ............................................................................ 80 Graphics Engine Control Register Description ................................................................................... 85
iii
VIII. Absolute Maximum Rating ................................................................................ 96 IX. DC Electrical Characteristic ................................................................................. 97
DC Characteristics ............................................................................................................................. 97 DAC Characteristics ........................................................................................................................... 98 DC Drive Characteristics ................................................................................................................... 98
X. AC Electrical Characteristic ................................................................................... 99
BIOS ROM Interface Timing SPEC. ................................................................................................... 99 ISA Bus Interface Timing SPEC. ...................................................................................................... 100 PCI Local Bus Interface Timing SPEC. ............................................................................................ 101 Memory Bus Interface Timing SPEC. ............................................................................................... 102 Color-Key PC Video & VAFC Interface Timing ............................................................................... 104 RAMDAC & Feature Connector Interface Timing ........................................................................... 104
XI. Timing Diagrams .................................................................................................. 105
BIOS ROM Read Cycle .................................................................................................................... 105 ISA Bus Interface Timing .................................................................................................................. 106 PCI Local Bus Interface Timing (32-bit data bus) ............................................................................ 107 16-Bit TXT CRT Cycle .................................................................................................................... 108 16-Bit CPU/GFX CRT/Shadow Frame Buffer Cycle ....................................................................... 109 32-Bit TXT CRT Cycle .................................................................................................................... 110 32-Bit CPU/GFX CRT/Shadow Frame Buffer Cycle ........................................................................ 111 16-Bit Read-Modify-Write Cycle ..................................................................................................... 112 32-Bit Read-Modify-Write Cycle ..................................................................................................... 113 Refresh Cycle Cycle(CAS Before RAS) .......................................................................................... 114 External Frame Buffer Interface Timing (16-bit) .............................................................................. 115 RAMDAC & Feature Connector Interface Timing ........................................................................... 116 Color-Key PC Video & VAFC Interface Timing ............................................................................... 117
XII. Appendix .............................................................................................................. 118
A. Monitor Specification .................................................................................................................. 118 B. TP6508 VGA Modes ................................................................................................................... 119 C. Rast Operation Code List ............................................................................................................. 121 D. Memory Address Table ............................................................................................................... 124 E. MCLK & VCLK Frequency Programming Table.......................................................................... 129 F. Pins Selection Configuration......................................................................................................... 131
iv
I. General Description
The TP6508 is an advanced single-chip flat panel VGA controller . It's used for notebook or portable computer system with simple operation and powerful features. Also it contains all of the functions and supports logic required to implement the IBM VGA display standards and enhanced display modes on LCD, PLASMA,EL panel and TV display at register and BIOS level compatiable. A simultaneous display technology is implemented in TP6508 to be used for CRT/Flat panel, LCD/ TV display. For minimum chip-count or board-space, it is designed to complete a video subsystem with only one 256kx16 DRAM(512K Bytes). This video subsystem can support all panel type without any glue logic or external frame buffer. Like general VGA graphics chips, the TP6508 includes CRT Controller (CRTC), Attribute Controller (ATRC), Graphic Controller (GFXC), Address Multiplexer (AMUX) , Sequential Controller (SEQC) and adds a Graphics Engine Controller (GEC) to provide VGA display functions and to speed up the system operation. With the deeper CRT FIFO , and the multiple level CPU command FIFO (Write Buffer) / Read Cache , the TP6508 supports higher system performance even in minimum memory configurations. In order to complete a video subsystem by two chips, VGA controller and DRAM, the TP6508 uses 208pin QFP to integrate Clock Generator(Dual frequency synthesizers), True-color RAMDAC, Display controller, Flat panel controller, Video-in interface, Graphics Engine Controller and Power management controller to minimizes the form factor requirement for VGA subsystem. In addition to an ISA bus connection, it can be connected directly to PCI standard local bus interface to provide additional graphics performance without any glue logic. TP6508 can support flat panel display, resolution up to 1024x768 mono, 800x600 hi-color, 640x480 true-color. Unlike on CRT, the pixels on a flat panel display are real,discrete entities of a fixed size. This results in problems when different display modes are mapped onto one panel. The TP6508 provides approach to keep the vertical resolution of the display mode constant but center the active display area vertically on the panel. The flat panel interface supports Monochrome/Color STN LCD panel, Color TFT LCD panel, PLASMA panel and, EL panel. Providing direct panel interface to (DD) Dual-panel,Dual-drive for color and monochrome and (SS) Single-panel,Single-drive (supports 8,9,12,15,16,18,24-bit data). For Single-panel/Single-drive panel which refresh data rate is not high, the TP6508 can set some of the video memory as the frame buffer for panel display to decrease video memory chip counts to one (a 256kx16DRAM).
P.1
When the TP6508 is interfaced to a dual-scan mono STN LCD panel , an additional DRAM isn't needed with the shadow frame buffer technology . This shadow frame buffer build in video memory that is used by the chipset to accelerate panel refresh rate without using high frequency clocks , thus reducing power, and allowing vertical refresh rates from 60 Hz to 160 Hz for improved contrast and freedom from flicker. The TP6508 serves as a DRAM controller for the display memory,it handle DRAM refresh, display refresh, display memory access by CPU and supply the control signal of DRAM with dualwrite or dual-cas. The TP6508 offers two types DRAM to make various memory configurations including of 512k , 1024k , 2048k memory size for different market. TP6508 support 256k x 4-bit , or 256k x 16-bit DRAM memory to simplify VGA system and implement high resolution display simultaneously. With Random Memory Cycle allocation skill and the multiple level CPU write buffer, the TP6508 provide better system performance and achieve zero wait state during memory write accesses. When using DRAM 256kx16 by 1 or DRAM 256kx4 by 4, memory size is 512k byte and data width is 16 bits. When using 256kx16 by 2 or 256kx4 by 8, memory size is 1M byte and data size is 32 bits. TP6508 can support the CRT display resolution up to 1024x768 256 color non-interlace, 800x600 hi-color,640x480 true color at 1M byte display memory. When using 256kx16 by 4 , memory size is 2M byte and data size is 32 bits. All display-memory can be linear addressing. The Video-in interface accept video signal from PC-video. Providing the power sequential control for flat panel . FPVCC signal is applied to the digital +5V voltage of flat panel, FPVEE signal is applied to the analog Driver's bias voltage of flat panel, and FPBACK signal is applied to the Invertor for the backlight of flat panel, their on/off sequence is programmable. Anotherway TP6508 providing intelligent control by timer to switch power mode (On including Cover-close,standby,suspend,Off) to save the power of TP6508 and Display. The TP6508 graphics chip has been designed to optimize cost/performance trade-off considerations. The Video clock rate depends upon the mode used, and is up to 135 MHz. The Memory clock input is optional and depends on the display DRAMs access-time . It can be up to 75 MHz.
P.2
II. Feature
. 208-pin single chip design . IBM VGA hardware compatible . Integrates RAMDAC - Support 24-bit True-color resolution - Up to 135 MHz pixel rate - Low power control - Implement Monitor-Sense feature . Integrates Clock Generator - Programmable dual frequency synthesizer - Up to 135 MHz clock rate for VCLK synthesier - Up to 75 MHz clock rate for MCLK synthesier - External Power-down mode Clock Source optional . Memory DRAM configuration support - Support symmetric or asymmetric RAS/CAS address DRAM - Support dual-CAS or dual-WE addressing DRAM - 512k Bytes Memory:four 256kx4-bit /one 256kx16-bit - 1M Bytes Memory:eigh 256kx4-bit /two 256kx16-bit - 2M Bytes Memory:sixteen 256kx4-bit/four 256kx16-bit . Bus support - ISA Bus with Zero-wait state assertion - 32-bit data width PCI Local Bus . Provide linear addressing - Relocation VGA memory address at over 1M-byte address location . Integrates STN panel support - Support Dual/single scan mono STN LCD Panel, up to 64 simultaneous grays - Support Dual/single scan color STN LCD Panel up to 64k simultaneous colors, and 613 visual color - Provide 8 and 16 bit panel interfaces . Integrates color TFT panel support - Support Normal or CRT-like TFT LCD panel - Support 9/12/15 or 18/24 bit panel interface, and up to 16.8M simultaneous colors . Support panel resolution up to 800x600 for STN and TFT LCD flat panel . Simultaneous Display operation - Simultaneous LCD and CRT display - Simultaneous PLASMA and CRT display - Simultaneous EL and CRT display - Simultaneous LCD and TV display . VGA BIOS decoding - Provide 64k-byte or 32k-byte VGA BIOS decoding
P.3
. Dual-scan STN Frame Buffer - Shadow Frame Buffer onto display memory for mono or color LCD panel - Pseudo Frame Buffer for color LCD panel (no additional DRAMs required) - External Frame Buffer for color LCD panel (external additional DRAMs required) . Provide PC Video interface - Provide VESA Advanced Feature Connector(VAFC) interface - Provide color-key PC video interface . High Performance architecture - Provide 4 stages CPU Write Buffer - Provide 8 stages Command FIFO for graphics engine access - Offer 20 stages CRT FIFO and 8 stages Attribute FIFO . Integrates hardware cursor function - 64 by 64 pixels (2-bit) - Offer Color 0,1,inversion and transparency operation . Windows performance-improvement feature - Bit block transfer (8/16/24 bit color mode) including of Image read/write - Color expansion (8/16/24 bit mode) - Line drawing (8/16/24 bit mode) - Rectangular clipping (8/16/24 bit mode) - Rectangular fill and Pattern fill(8/16/24 bit mode) . Graphics Engine I/O command addressing - Programmable I/O base command - Memory mapping I/O command . Intelligent Power Management - Built-In Power Management controller - Multiple level power down modes (On/Standby/Suspend/Off mode) - Automatic activity monitoring - Flexible mode transition Control (Pin control/Timer out/Register programming /VGA access and Keyboard request trigger return) - Automatic flat panel power sequencing - Programmable slow refresh rate . Enhanced mode includes: - 132x25 or 132x44 text mode - 640x480/256 colors (Windows acceleration mode support optional) - 640x480/65536 colors (Windows acceleration mode support optional) - 640x480/16.8M colors (Windows acceleration mode support optional) - 800x600/16 colors - 800x600/256 colors (Windows acceleration mode support optional) - 800x600/65536 colors (Windows acceleration mode support optional) - 800x600/16.8M colors - 1024x768/16 colors - 1024x768/256 colors (Windows acceleration mode support optional) - 1024x768/65536 colors (Windows acceleration mode support optional) - 1280x1024/16 colors - 1280x1024/256 colors (Windows acceleration mode support optional) - 1600x1280/16 colors interlace display mode
P.4
III. Pin Configurations
ISA Bus Interface Connections
1111111111111111111111 111111111111111111111111111111 5555555444444444433333 333332222222222111111111100000 6543210987654321098765 432109876543210987654321098765 R O A A A A A A A A A A M M M M M M M M M M M M M M M M M M C C WR M M M M M M M M M M M M M M M M M M A E A A A A A A A A A A B B V B B V B B B B B B B B B B B B A A E A C C C CC C CC C C C CC C V C C V S A 9 8 7 6 5 4 3 2 1 0 DD D DD S DD D D DD D DD DD D S S B S D D D DD D DD D D D DD D DD D S A B / / / / / / / / / / 1 1 D 1 1 S 1 1 9 8 7 6 5 4 3 2 1 0 B B * B 1 1 1 1 1 1 9 8 7 6 5 4 3 2 D1 0 S * * V C CC C CC C CC 5 4 B 3 2 B 1 0 L H / * 5 4 3 2 1 0 / / / / / / / / C/ / C RF FF F FF F FF * * W / / / / / / VV V V V VV V V V 0 G GG G GG G GG / / E V V V V V V GG G G B B B B B B 876543210 WC B R R R R G G 5 4 3 2 7 6 5 4 3 2 ///////// EA H 5 4 3 2 7 6 / / / / / / / / // L T A OER 2 I L BS * / / / / / / VV V V V VV V V E V S D S CC X S B LB V V V GV V P P P P P P P P P V # # # # # # # A# ** P P P RP P 8 7 6 5 4 3 2 1 0 I # D 1 1 1 D1 9 # 3 2 1 Y0
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
WEA*/WEAH* MVDDA CASAH*/CASA* CASAL*/WEAL* MVSSA MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 OFF/EXVCLK/EPROM* SA2 SA3 CVDD2 SA4 SA5 CVSS2 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 LA17 LA18 LA19 LA20 LA21 LA22 AVSS2 XTALI/EXMCLK/OSC XTALO AVDD2 AVDD3 RESET AVSS3
TP6508
VP14/CASCL*/WECL*/VR6 VP15/CASCH*/CASC*/VR7 WEC*/WECH*/PCLK VRDY/RASC*/KEY VCLK/OEC*/VR1 CA9/VG0 CA8/VG1 CA7/P23 CA6/P22 CA5/P21 CA4/P20 CA3/P19 CA2/P18 CA1/P17 CA0/P16 DVSS2 P15 P14 P13 P12 P11 P10 P9 P8 CVDD1 P7 P6 CVSS1 P5 P4 P3 P2 P1 P0 SHFCLK M LP FLM DVDD HSYNC VSYNC DVSS1 FPVCC FPVEE/FPBACK RED AVDD1 GREEN BLUE AVSS1 RSET FPBACK/VB1 ACTI/VB0
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
M IE R I OM O B S B MO I B I B MB CC B V BS S SS S SV E R OV O L M V RE V SS V D E MS 1 1 O S A M D WS R A C I A H D D D D D D S S S D S S S S S S S S S S N N N N N N N N D F R S N N N N N 6 6 WA L WY*R S D 2 S R E E 1 1 1 1 1 1 S D D D A D D D D D D D D S C CC C C CC C 1 * * 1 CC C CC * * S 1 E * * * 2 * 3 * QN * 5 4 3 2 1 0 3 9 8 2 0 7 6 5 4 3 2 1 0 4 1234567891111111111222222222233333333 334444444444555 0123456789012345678901234567 890123456789012
P.5
PCI Local Bus Interface Connections
1111111111111111111111111111111111111111111111111111 5555555444444444433333333332222222222111111111100000 6543210987654321098765432109876543210987654321098765 R O A A A A A A A A A A M M M M M M M M M M M M M M M M M M C C WR M M M M M M M M M M M M M M M M M M A E A A A A A A A A A A B B V B B V B B B B B B B B B B B B A A E A CC CCCC CCC CCCC CV CCV S A 9 8 7 6 5 4 3 2 1 0 DDDD DS D DDDD DD DDDDD S S B S DD DDDD DDD DDDD DD DDS A B / / / / / / / / / / 1 1 D1 1 S 1 1 9 8 7 6 5 4 3 2 1 0 B B * B 1 1 1 1 1 1 9 8 7 6 5 4 3 2 D 1 0 S * * V CCC CCCC CC 5 4 B 3 2 B 1 0 L H/ * 5 4 3 2 1 0 / / / / / / / / C / / C RF F F F F F F F F * * W / / / / / / VVV VVVV V VV 0 GGG GGGG GG / / E V V V V V V GGG GB B B B B B 876543210 WC B R R R R G G 5 4 3 2 7 6 5 4 3 2 ///////// EAH 5 4 3 2 7 6 / / / / / / / / // L T A OE R 2 I L BS* / / / / / / VVV VVVV V VE V S D S CCX S B LB V V V GV V P P P P P P P P P V # # # # # # # A# ** P P P RP P 8 7 6 5 4 3 2 1 0 I # D 1 1 1 D1 9 # 3 2 1 Y0
157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
WEA*/WEAH* MVDDA CASAH*/CASA* CASAL*/WEAL* MVSSA MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 OFF/EXVCLK NC NC CVDD2 NC NC CVSS2 NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC CLK AVSS2 XTALI/EXMCLK/OSC XTALO AVDD2 AVDD3 RST# AVSS3
TP6508
VP14/CASCL*/WECL*/VR6 VP15/CASCH*/CASC*/VR7 WEC*/WECH*/PCLK VRDY/RASC*/KEY VCLK/OEC*/VR1 CA9/VG0 CA8/VG1 CA7/P23 CA6/P22 CA5/P21 CA4/P20 CA3/P19 CA2/P18 CA1/P17 CA0/P16 DVSS2 P15 P14 P13 P12 P11 P10 P9 P8 CVDD1 P7 P6 CVSS1 P5 P4 P3 P2 P1 P0 SHFCLK M LP FLM DVDD HSYNC VSYNC DVSS1 FPVCC FPVEE/FPBACK RED AVDD1 GREEN BLUE AVSS1 RSET FPBACK/VB1 ACTI/VB0
104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53
D E F BC B CI B B PS C C RI T V B B VB A AA A A A A A V B DV A A A A A A A A B A RRS V S E E B A A A A A A V V D D D D D D D D D E S S D D D D D D D D E MD D E S T R R P E D D D D D D S A A D E A A A A A A A A S 3 3 2 2 2 2 2 2 D 3 E S 2 2 2 2 1 1 1 1 2 E Y Y L S ON R R A 1 1 1 1 1 1 1 S D D D 0 D D D D D D D D S 1 0 9 8 7 6 5 4 1 # L 1 3 2 1 0 9 8 7 6 # # # # # 2 P C# # R # 5 4 3 2 1 0 3 9 8 2 # 7 6 5 4 3 2 1 0 4 1234567891111111111222222222233333333334444444444555 0123456789012345678901234567890123456789012
P.6
IV. Functional Block Diagram
System Block Diagram
DISPLAY MEMORY Frame Buffer DRAM-A
256 x 16bit
H O S T L O
RGB TO NTSC/PAL ISA BUS PCI BUS PC Video Interface Optional
DRAM-B
256 x 16bit
DRAM-C
256 x 16bit (512KB)
(512KB/1MB/2MB)
TP6508
Internal Built in Clock Generator
PC Video
G I C
COLOR/MONO LCD/PLASMA/EL Panel Internal built-in Ture-Color DAC
TV Encoder
PANEL
TV
VGA MONITOR NTSC/PAL SYSTEM
1280 X 1024 / 256 , 800 X600 / 16.8M COLORS FLAT PANEL/CRT DISPLAY SYSTEM
[SP508B05.DS4 86/04/15 L.R.Y.]
P.7
VGA Block Diagram
Address.. Data..
Hsync.. Vsync..
AMUX.. Decoder.. CRTC..
ISA/LOCAL BUS..
TP6508
MD.. MA..
DISPLAY.. MEMORY..
512K DRAM
CRT/ATRR FIFO
Shadow. Frame Buffer.
Graphics. Command. FIFO. Engine. Cntl.. PC Video. Cntl.. WRITE.. BUF..
VLCK..
2MB Memory
Video Interface. Video Processer. MPEG Decoder.
Graph.. Cntl.. SEQ..
Power. Management. Cntl..
C.G.. Dual Frequency. Synthesizer.. MCLK..
Reference. Clock. Source. 14.318MHz..
Panel. Cntl..
FLAT .. PANEL..
R..
Attrib.. Cntl..
Data..
DAC..
Ture-Color.. Pallette..
G.. B..
CRT.. Display..
[SP508B01.DS4 84.08.21]
P.8
True-Color Palette DAC Block Diagram
Mode control
Pseudo Mode HiCOLOR-15TM HiCOLOR-16TM HiCOLOR-24TM
GP0-GP23
P0-P23
DACOff
VREF
MSOff
Power
Sel 8 256*18 SRAM
LATCH
24(16/15)
Controller
COMPARE
SENSE
MUX
PIXEL READ MASK REG.
DAC
R
8 MUX
DAC
G
8
8
ADDRESS REGISTER
8
MUX
DAC
B
8
COMMAND REGISTER
CNTL
R
8
G
8
B
8
BUS CONTROL
RD0-RD7
/RD
/WR
[SP508B02.DS4 85/03/11
L.R.Y.]
P.9
Dual Frequency Synthesizer Block Diagram
VD0-6 VCLKD VCLKN VCLKP VCLKO 7 7 1 1 INPUT LATCH 1 VP VO INPUT VN0-6 DIVIDER 1 PHASE COMP 1 FEEDBACK DIVIDER 1 VP
DIVIDER /2 VO DIVIDER /2
CHARGE PUMP
VCO 1 /en OUTPUT Buffer
VCLK
C.G. POWER PowerDown XTALI XTALO MANAGEMENT CONTROL OSC BUFFER OUTPUT Buffer MMD0-6 INPUT MCLKD MCLKN MCLKP MCLKO 7 7 1 1 DIVIDER 2 INPUT LATCH 2 MP MO FEEDBACK MN0-6 DIVIDER 2 DIVIDER /2 PHASE COMP 2 CHARGE PUMP /en VCO 2 MO DIVIDER /2 MCLK 14.318MHz
MP
[SP508B03.DS4 85/03/11 L.R.Y.]
P.10
Panel Controller Block Diagram
Display Memory (Frame Buffer)
LINE BUFFER
SUM to GRAY DITH 1 M U 6 6 M FP0-23 U 6 6 M U RGBI emulation 6 6
[SP508B04.DS4 85/03/11 L.R.Y.]
1 Amplitute 1 Modulator
D F F Dither
D F F Amplitute Modulator PANEL INTERFACE
X
D F F Dither
D Amplitute F F Modulator
Flat Panel
X
D F F Dither
D Amplitute F F Modulator
X
P.11
Graphics Engine Diagram
Address Path
LX(10:0) LY(10:0) SOURCE X SOURCE Y X(10:0) Y(10:0)
Line Drawing Address Caculation ADR MUX.
Map Enable
Clipping
SOURCE X SOURCE Y DESTIN. X DESTIN. Y PATTERN X PATTERN Y
Bit Block Address
BX(10:0) BY(10:0)
Address Translation
ROW ADR(9:0) COL ADR(9:0)
Data Path
MD[31:0] SD' [31:0]
DATA MUX.
Alignment
Line Drawing Color Select
Source FIFO
HOST Data Output
SD[31:0]
Foreground Color Background Color MD[31:0]
MUX. 256 ROP.
MD[31:0]
Pattern FIFO
[SP508B12.DS4
85.08.21]
P.12
Memory Configuration Block Diagram
512 K MEMORY DRAM(S) CONFIGURATION
VGA DRAM
1024K MEMORY DRAM(S) CONFIGURATION
A.
VGA
DRAM
RAS0* CAS0* MD[7:0]
256KX4
RAS0* CAS0* M0D[15:0]
256KX4
256KX4
256KX4
CAS1*
256KX4
256KX4
RAS0* CAS1* MD[15:8]
256KX4
RAS0* CAS2* MD[31:16]
256KX4
256KX4
256KX4
CAS3*
256KX4
256KX4
VGA
DRAM
B.
RAS0* CAS0* MD[7:0]
C.
VGA RAS0* CAS0* CAS1* MD[7:0] MD[15:8]
DRAM
512KX8
256KX16
CAS1* MD[15:8]
512KX8
CAS2* CAS3* MD[23:16] MD[31:24]
256KX16
[SP508B06.DS4 84/05/23]
P.13
2048K MEMORY DRAM(S) CONFIGURATION
A.
VGA
DRAM
RAS0* CAS0* MD[15:0]
256KX4
256KX4
256KX4
256KX4
CAS1*
256KX4
256KX4
256KX4
256KX4
RAS0* CAS2* MD[31:16]
256KX4
256KX4
256KX4
256KX4
CAS3*
256KX4
256KX4
256KX4
256KX4
RAS1*
B.
VGA
DRAM
C.
VGA RAS0* CAS0* CAS1* MD[15:0]
DRAM
RAS0* CAS0* CAS1* MD[15:0]
512KX8
512KX8
256KX16
256KX16
RAS0* CAS2* CAS3* MD[31:16]
512KX8
512KX8
CAS2* CAS3* MD[31:16]
256KX16
256KX16
RAS1*
[SP508B06.DS4 84/05/23]
P.14
V. Pin Descriptions
* ISA Bus Interface (54 pins)
Symble
SD[15:0]
Type
I/O
Drive
8maR
Pin Number
33,34,35,36,37 38,40,41,44,45 46,47,48,49,50,51 195,194,193,192,191, 190,189,188,187,186, 185,183,182,180,179, 21,43 28,201,200,199,198, 197,196
Active
True
Function
These signals provide 16 data bits transfer on ISA bus with system microprocessor. Address Bit 16 Through 0 are used to address frame buffer and I/O ports with TP6508.
SA[16:2] SA[1:0]
I (I/O) I
-
True
LA[23:22] A21 A20 LA[19:17] AEN
I I (I/O) I I (I/O) I (I/O) I I
-
True
-
31
High
ALE SBHE*
-
22 32
High Low
IORD* IOWR*
I (I/O) I (I/O) I
-
27 25
Low Low
MEMR*
-
11
Low
MEMW*
I
-
23
Low
IORDY* IOCS16*
OT OT (I/O) OT (I/O) I/S
12maR 12maR
24 18
Low Low
MEMCS16* RESET*
12maR -
19 207
Low Low
IRQ REF*
OT (I/O) I
8maR -
30 10
Low Low
Address Bit 23 Through 17 are used to address frame buffer and I/O ports with TP6508. In general ,these signals are not gated address LA[19:17] A high active signal used to detect the TP6508 from the I/O channel to avoid a disturbance from the DMA controller. This signal is used to latch those ungated address bus. It indicates and enables transfer of data on the high byte of data bus and is used with A0 to distinguish between high and low byte. I/O read signal comes from a host microprocessor to read data from TP6508 control. I/O write signal comes from a host microprocessor to read data from TP6508 control registers. Memory read signal comes from a host microprocessor to read data from video memory. Memory write signal comes from a host microprocessor to read data from video memory. This signal is driven low by TP6508 to lengthen the memory or I/O accessed cycle. This signal is driven low to indicate that the TP6508 can execute an I/O operation at the address currently on the 16-bit bus mode. This signal drives a 16-bit memory cycle for 16-bit bus data transfer. This pin is connected to the signal that was inverted from the system board to reset the TP6508. The vertical retrace interrupt. This signal is driven by system mother board logic and is used to indicate a memory refresh cycle is in operation. This signal is driven by TP6508 to short the memory accessed cycle for improving system performance. P15
OWS*
OT (I/O)
8maR
20
Low
* PCI Local Bus Interface
Symble
AD[31:0]
( 48 pins )
Pin Number
1,2,3,4,5, 6,7,8,13,14, 15,16,17,18,19,20, 33,34,35,36,37 38,40,41,44,45 46,47,48,49,50,51 10,21,32,43
Type
I/O
Drive
8maR
Active
True
Function
Address and Data are multiplexed on the same PCI Bus interface. A Bus transaction consists of an address phase followed by one or more data phase.
C/BE[3:0]#
I
-
True
PAR
OT (I/O) I OT
4maR
31
True
FRAME# TRDY#
12maR
22 24
Low Low
IRDY#
I
-
23
Low
IDSEL RESET# CLK DEVSEL#
I I/S I OT (I/O)
12maR
11 207 201 25
High Low True Low
STOP#
OT (I/O) O/T (I/O)
4maR
27
Low
PERR#
8maR
29
Low
SERR#
O/T (I/O)
8maR
30
Low
Bus Command and Byte Enable are multiplexed on the same PCI Bus interface. During the address phase of a transaction, they define the Bus Command. During the data phase , they are used as Byte Enable. Parity is even part across AD[31:0] and C/BE[3:0]#. Parity generation is required by all PCI agents. This input signal is used to indicate the beginning and duration of an access. This signal is driven to indicate TP6508's ability to complete the current data phase. It is used in conjunction with IRDY#. This input signal is to indicate Bus master's ability to complete the current data phase. It is used in conjunction with TRDY#. This signal is used as a chip select during configuration read and write access. This signal is used to reset the TP6508 video device into initial state. This is the timing reference for TP6508 when connected to PCI Local Bus. This signal is driven to indicate that TP6508 video device has been selected . So TP6508 has decoded its address as the target of the current access. This signal is output to indicate that TP6508 is requesting the master to stop the current transaction. This signal is used for the reporting of data parity erros. PERR# will be driven high for one clock before being tristated as with all sustained tristate signals. This signal is used for the reporting of system erros.
P16
* Display Memory Interface (82 pins)
Symble
AA9 AA[8:0] CA[9:8] CA[7:0] MAD[15:0]
Type
I/O I/O/U I/O O I/O/U
Drive
4maR 4maR 4maR 4maR 4maR
Pin Number
154,153,152,151,150, 149,148,147,146,145 99,98,97,96,95, 94,93,92,91,90 177,176,175,174,173, 172,171,170,169,168, 167,166,165,164,163 162 144,143,141,140,138, 137,136,135,134,133, 132,131,130,129,128, 127 122,121,120,119,118, 117,116,115,114,113, 112,111,110,109,107, 106
Active
True
Function
Display memory address bit 9 to 0 for DRAMs A and B. A pull-high mechanism gives a default high value in those configuration data. Display memory address bit 9 to 0 for DRAMs C. These pins are used to transfer data between the TP6508 and display memory, DRAM A. A pullhigh mechanism gives a default high value in those configuration data. These pins are used to transfer data between the TP6508 and display memory, DRAM B.
True True
MBD[15:0]
I/O
4maR
True
MCD[15:0]
I/O
4maR
True
RASA* RASB* RASC* CASAL*/WEAL*
O O I/O O
4maR 4maR 4maR 4maR
156 123 101 160
Low Low Low Low
CASAH*/CASA* CASBL*/WEBL* CASBH*/CASB* CASCL*/WEAL*I/O CASCH*/CASC* WEA*/WEAH*
O O O 4maR I/O O
4maR 4maR 4maR
159 126 125 104
Low Low Low Low Low Low
4maR 4maR
103 157
WEB*/WEBH* WEC*/WECH* OEAB* OEC*
O O O I/O
4maR 4maR 8maR 4maR
124 102 155 100
Low Low Low Low
These pins are used to transfer data between the TP6508 and frame buffer memory, DRAM C. When a frame buffer DRAM isn't requireed, this bus may optionall be used to input up to 24 bits of RGB data from the external PC-Video subsystem(device). Row address strobe for latching 10-bit row address signal into display memory, DRAM A.. Row address strobe for latching 10-bit row address signal into display memory, DRAM B.. Row address strobe for latching 10-bit row address signal into display memory, DRAM C.. Column address strobe for DRAM A lower byte in dual-CAS application. In dual-WE application, it is used as write enable signal for DRAM A lower byte. Column address strobe for DRAM A upper bytein dual-CAS application. Column address strobe for DRAM B lower bytein dual-CAS application. Column address strobe for DRAM B upper byte.in dual-CAS application. Column address strobe for DRAM C lower bytein dual-CAS application. Column address strobe for DRAM C upper bytein dual-CAS application. Write enable signal for DRAM A in dual-CAS application. In dual-WE application, it is used as write enable signal for DRAM A upper byte. Write enable signal for DRAM Bin dual-CAS application. Write enable signal for DRAM Cin dual-CAS application. Data output enable signal for DRAM A and DRAM B. Data output enable signal for DRAM C.
P17
* CRT Output interface (6 pins)
Symble
RED GREEN BLUE RSET
Type
Analog Output Analog Output Analog Output Analog Output
Drive
20ma 20ma 20ma 10ma
Pin Number
60 58 57 55
Active
-
Function
These three analog outputs are generated by TP6508's internal build-in DAC and it supplies current corresponding to the red , green , blue value of pixel being displayed. This pin input is used as the internal build-in RAMDAC voltage reference. A setting resister is required between this pin and AVSS1 determines the full-scale output of each DAC. Vertical retrace synchronization signal drives the CRT monitor. Horizontal retrace synchronization signal drives the CRT monitor.
-
VSYNC HSYNC
O O
12maR 12maR
64 65
True True
* Clock Input Interface (4 pins)
XTALI EXMCLK OSC I I I 203 True True True The pin serves as the crystal input. External memory clock input. It requires an input frequency of 14.318MHz with a duty cycle of 50+/-5%.This input pin supplies the reference frequency for the Dual-frequency Synthesizer . The pin serves as the crystal output . External video clock input It is a optional input from STANBY pin. Refresh clock input for DRAMs under into OFF mode (VESA DPMS).
XTALO EXVCLK 32KHZ
O I (I/O) I (I/O)
-
204 178 154
True True True
* MISC. Pins (2 pins)
ROMCS* O (I/O) 8maR 29 Low VGA BIOS ROM enable signal for ISA bus, it generated by HM86509 when the 32k-byte memory location from C0000 to C7fff or the 64k-byte memory domain setting by extended registers is selected. This pin is intended for testing. It can be redefined as other useful function pin at the combination switch type of description in extended register Hex CC .
TEST
I/O
4maR
178
True
P18
* Flat Panel Interface (28 pins)
Symble
SHFCLK(CL2) LP(CL1) PHSYNC DE
Type
O OT
Drive
12maR 8maR
Pin Number
70 68
Active
True High True High
Function
This signal is used to driver the flat panel shift clock . This signal is used to drive the flat panel line clock for LCD panels or the horizontal sync for PLASMA/EL panels and some TFT panels. It can also do as the display enable signal (DE) for flat panel. This signal is used to start a new frame on flat panels for LCD panels or the vertical sync for PLASMA/EL panels and some TFT panels. This signal is used to provide the AC inversion for flat panels to prevent a chemical damage. It can also do as the display enable signal (DE) for flat panel. These signals contain RED/GREEN/BLUE color data for 9/12/18/24 bit interface TFT-color LCD panels.
FLM PVSYNC M DE
OT
8maR
67
High True True High
O
8maR
69
P[23:16] P[15:0]
O O
4maR 8maR
SLD[7:0] SUD[7:0] LD[3:0]/ED[3:0]
O O O
8maR 8maR 8maR
97,96,95,94,93, 92,91,90 88,87,86,85,84, 83,82,81,79,78, 76,75,74,73,72,71 75,76,78,79,85, 86,87,88 71,72,73,74,81, 82,83,84 75,76,78,79
True
True True True True
UD[3:0]/OD[3:0]
O
8maR
71,72,73,74
True True
* Power Management Pins (5 pins)
ACTI I (I/O) O 53 High
These signals contain the lower data for color STN LCD panels . These signals contain the upper data for color STN LCD panels . These signals contain the lower data for gray dual-scan LCD panels . These signals contain the even data for gray PLASMA/EL panels . These signals contain the upper data for gray dual-scan LCD panels . These signals contain the odd data for gray PLASMA/EL panels . The ACTI output is an active high signal that is driven high every time a valid VGA access (memory or I/O read/write). This signal is part of the flat panel power-down sequencing and should be connected to the flat panel LOGIC power enable . ( default = 1 ) This signal is part of the flat panel power-down sequencing and should be connected to the flat panel BIAS power enable . ( default = 1 ) This signal is part of the flat panel power-down sequencing and should be connected to the flat panel BACKLIGH enable . ( default = 0 ) This input is used to force TP6508 into Off mode enable. This pin can also redefined as an output to indicate the active status . It may be also configed as other function- by extended register.
FPVCC
8maR
62
High
FPVEE
O
8maR
61
High
FPBACK
O
8maR
54
High
OFF
I/O
4maR
178
High
P19
Flat Panel Interface Table
Mono Color Color Color LCD LCD LCD* LCD Pin Dual-scan Single-scan Dual-scan Dual-scan Pin Name Number STN STN STN STN 8-bit 70 68 67 69 71 72 73 74 75 76 78 79 81 82 83 84 85 86 87 88 90 91 92 93 94 95 96 97 SHFCLK SCLK LP FLM M P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22 P23 LCLK FLM MDL UD3 UD2 UD1 UD0 LD3 LD2 LD1 LD0 16-bit CL2 CL1 FLM M SUD7 SUD6 SUD5 SUD4 SUD3 SUD2 SUD1 SUD0 SLD7 SLD6 SLD5 SLD4 SLD3 SLD2 SLD1 SLD0 8-bit CL2 CL1 FLM M SUD7 SUD6 SUD5 SUD4 SUD3 SUD2 SUD1 SUD0 16-bit CL2 CL1 FLM M SUD7 SUD6 SUD5 SUD4 SLD7 SLD6 SLD5 SLD4 SUD3 SUD2 SUD1 SUD0 SLD3 SLD2 SLD1 SLD0 Color LCD TFT
9/12/16-bit
Color LCD TFT 18/24-bit DCLK LP/HS
Gray PLASM 8-bit CLK
Gray EL 8-bit VCLK
DCLK LP/HS FLM/VS DE B0 B1 B2 B3 B4 G0 G1 G2 G3 G4 G5 R0 R1 R2 R3 R4
HSYNC HS VS DE
FLM/VS VSYNC DE B0 B1 B2 B3 B4 B5 B6 B7 G0 G1 G2 G3 G4 G5 G6 G7 R0 R1 R2 R3 R4 R5 R6 R7 OD3 OD2 OD1 OD0 ED3 ED2 ED1 ED0
DISPTMG
OD3 OD2 OD1 OD0 ED3 ED2 ED1 ED0
* : Color Dual-scan STN LCD Panel with external frame buffer [84.05.29 508PNL.TBL]
P20
Symble
Type
Drive
Pin Number
Active
Function
* Video Interface (26 pins)
VR[7:0] VG[7:0] VB[7:0] KEY PCLK VP[15:0] I/O I/O I/O I/O O I/O 4maR 4maR 4maR 4maR 4maR 4maR 103,104,122,121,120, 119,100,154 118,117,116,115,114, 113,98,99 112,111,110,109,107, 106,54,53 101 102 103,104,122,121,120, 118,117,116,115,114, 113,112,111,110,109, 107 101 119 106 100 True True True True True True Red data for the Video-In input by external PCVideo system. Green data for the Video-In input by external PC-Video system. Blue data for the Video-In input by external PCVideo system. Color key signal for the Video-In input by external PC-Video system. Pixel clock input of the Video-In interface by external PC-Video system. VAFC interface video pixel data output.
VRDY GRDY EVID# VCLK
I O I I
4maR -
High High Low True
VAFC interface video system ready signal. VAFC interface graphics system ready signal. VAFC interface enable video signal. VAFC interface video input clock.
* Power Pins (25 pins)
AVDD1 AVDD2 AVDD3 BVDD[1:2] CVDD[1:2] DVDD MVDDA MVDDB MVDDC AVSS1 AVSS2 AVSS3 BVSS[1:4] CVSS[1:2] DVSS[1:2] MVSSA MVSSB MVSSC 59 205 206 9,42 80,181 66 158 142 108 56 202 208 12,26,39,52 77,184 63,89 161 139 105 +5V +5V +5V +5V +5V +5V +5V +5V +5V Ground Ground Ground Ground Ground Ground Ground Ground Ground Internal DAC analog power. Internal MCLK frequency Synthesizer power. Internal VCLK frequency Synthesizer power. Host bus interface power. Core logical power. Digital pads output power. Memory bus A interface power. Memory bus B interface power. Memory bus C interface power. Internal DAC analog ground. Internal MCLK frequency Synthesizer analog ground. Internal VCLK frequency Synthesizer analog ground. Host bus interface ground. Core logical ground. Digital pads output ground. Memory bus A interface ground. Memory bus B interface ground. Memory bus C interface ground.
*** Descript of Type term
O : Output I : Input I/O : Birdirectional OT : Output Tri-state I/S : Schmitt-trigger Input U : Internal passive pull-up P21
* Host Bus Interface Table
Pin Type I/O I/O I/O I/O I/O Input Input Input Input I/O Input I/O Input Input I/O I/O I/O I/O Input Input I/O Input Input OT I/O I/O Pin Number 20 19 18 43 32 21 10 201 28 29 30 53 54 207 22 31 11 23 24 25 27 12maR 12maR 4maR 4maR 8maR 8maR 8maR 8maR 4maR 4maR Pin Drive ISA Bus PCI 32-Bit Local Bus AD[15:0] AD16 AD17 AD18 AD[31:19] SA0 SBHE* SA1 REF* SA[19:2] SA20 SA21 SA22 SA23 ROMCS* IRQ (ACTI) (FPBACK) RESET ALE AEN MEMR* MEMW* IORDY* IOWR* IORD* [86.04.15 PERR# SERR# (ACTI) (FPBACK) RST# FRAME# PAR IDSEL IRDY# TRDY# DEVSEL# STOP# 508BUS.TBL]
P22
8maR 8maR 8maR 8maR 8maR
SD[15:0] OWS MEMCS16* IOCS16*
CBE0# CBE1# CBE2# CBE3# ROMA[17:0] ROMOE* CLK
* Pin List
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 Pin Dr i v e
8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR
Pin Type
I/O I/O I/O I/O I/O I/O I/O I/O Power I I Ground
8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR
I/O I/O I/O I/O I/O I/O I/O I/O I I I OT I/O Ground
12maR 12maR 12maR
I/O I I/O I/O I/O I
Pin Name AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 BVDD1 C BE 3 # IDSEL BVSS1 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 C BE 2 # FRAME# IRDY# TRDY# DEVSEL BVSS2 STOP PERR# SERR# PAR C BE 1 # AD15 AD14 AD13 AD12 AD11 AD10 BVSS3 AD9 AD8 BVDD2 C BE 0 # AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 BVSS4
Other Name(s) (ISA Bus)
Pin # 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Pin D r ive
8maR 8maR 10ma
Pin Type
I/O I/O
Analog Output
Ground 20ma 20ma
Analog Output Analog Output
Pin Name ACTI FPBACK RSET AVSS1 BLUE GREEN AVDD1 RED FPVEE FPV C C DVSS1 VSYNC HSYNC DVDD FLM LP M SHFCLK P0 P1 P2 P3 P4 P5 CVSS1 P6 P7 CVDD1 P8 P9 P10 P11 P12 P13 P14 P15 DVSS2 P16 P17 P18 P19 P20 P21 P22 P23 VG1 VG0 VR1 KEY PCLK VR7 VR6
Other
Name(s)
VB0,SDA,CSYNC VB1,SCL,CSYNC
Power 20ma 20ma 20ma 12maR 12maR 8maR 8maR 8maR 12maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR
Analog Output
REF* MEMR*
O O Ground O O Power OT OT O O O O O O O O Ground O O Power O O O O O O O O Ground O O O O O O O O I/O I/O I/O I/O O I/O I/O
FPBACK
CSYNC
IOCS16* MEMCS16* OWS SA1 ALE MEMW* IORDY* IOWR* IORD* LA23 ROMCS* IRQ AEN SBHE* SD15 SD14 SD13 SD1 SD11 SD10 SD9 SD8
8maR 8maR 4maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR
I/O I/O I/O I/O I/O I/O Ground I/O I/O Power I I/O I/O I/O I/O I/O I/O I/O I/O Ground
4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR
CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9 VCLK,OEC* VRDY,RASC* WEC*,WECH* VP15,CASCL*,WECL* VP15,CASCH*,CASC*
SA0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
8maR 8maR 8maR 8maR 8maR 8maR 8maR 8maR
P23
Pin # 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156
Pin Dr i v e
4maR 4maR
Pin Type
Ground I/O I/O Power
4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Ground
4maR 4maR
I/O I/O Power
4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 8maR 4maR
I/O I/O I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O O O
Pin Name MVSSC VB2 VB3 MVDDC VB4 VB5 VB6 VB7 VG2 VG3 VG4 VG5 VG6 VG7 VR2 VR3 VR4 VR5 RASB* WEB* CASBH CASBL* MBD0 MBD1 MBD2 MBD3 MBD4 MBD5 MBD6 MBD7 MBD8 MBD9 MBD10 MBD11 MVSSB MBD12 MBD13 MVDDB MBD14 MBD15 AA0 AA1 AA2 AA3 AA4 AA5 AA6 AA7 AA8 VR0 OE A B * RASA*
Other
Name(s)
EVID#,MCD0 VP0,MCD1
VP1,MCD2 VP2,MCD3 VP3,MCD4 VP4,MCD5 VP5,MCD6 VP6,MCD7 VP7,MCD8 VP8,MCD9 VP9,MCD10 VP10,MCD11 GRDY,MCD12 VP11,MCD13 VP12,MCD14 VP13,MCD15
WEBH*,AA9 CASB* WEBL*
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 32KHZ
Pin # 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208
Pin D r ive
4maR
Pin Type
O Power
4maR 4maR
O O Ground
4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR
I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O/U I/O I/O I/O Power
4maR 4maR
I/O I/O Ground
4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR 4maR
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
Pin Name WEA* MVDDA CASAH* CASAL* MVSSA MAD0 MAD1 MAD2 MAD3 MAD4 MAD5 MAD6 MAD7 MAD8 MAD9 MAD10 MAD11 MAD12 MAD13 MAD14 MAD15 OFF ROMA0 ROMA1 CVDD2 ROMA2 ROMA3 CVSS2 ROMA4 ROMA10 ROMA5 ROMA11 ROMA6 ROMA9 ROMA7 ROMA8 ROMA12 ROMA13 ROMA14 ROMA15 ROMA16 ROMA17 R OM OE CLK AVSS2 XTALI XTALO AVDD2 AVDD3 RST# AVSS3
Other
WEA H *
Name(s)
CASA* WEAL*
EXVCLK SA2 SA3
SA4 ,SA5
SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 LA17 LA18 LA19 LA20 LA21 LA22
4maR
I/O I Ground I
EXMCLK,OSC
-
O Power Power I/S Ground
RESET
P24
VI. Function Descriptions
The TP6508 contains seventeen major functional modules. There are; Host bus interface , Sequencer Control , CRT Controller, Attribute Controller , Graphics Controller , Address Multiplexer , CRT FIFO , Attribute FIFO , Write Buffer , Command FIFO ,Dual frequency Synthesizer , True-Color Palette , Graphics Engine Controller , PC Video Controller , LCD line buffer , Panel Controller , Power Management controller. The main difference between standard VGA and TP6508 is Graphics Engine Controller. We will introduce detail description on this part of the whole function. The following is an overview of the major elements of the TP6508.
Host Bus Interface
In addition to an ISA bus connection , it can be connected directly to PCI standard local bus interface to provide additional graphics performance without any glue logic .
* ISA Bus
TP6508 supports 16-bit ISA Bus with a high integrated bus interface that no additional logical is require . The TP6508 executes either 8-bit or 16-bit I/O and memory accesses .
* PCI Local Bus
TP6508 can directly connect to 32-bit PCI local bus without any additional logic to support its multiplexed address and data pins, at speeds of up to 33MHz. The TP6508 supports 32-bit data width accesses with memory burst mode , fast back-to-back , byte merge function . It also provides 256k BIOS ROM support and transfers ROM data through VGA to PCI bus .
Sequencer Controller (SEQC)
The Sequencer Controller includes a timing generator. The timing generator produces the basic timing sequence control for the CRTC , ATC, GFXC. It manages the display memory and provides an arbitration for CRT, CPU and Refresh requests. With a deeper CRT FIFO design, the TP6508 performs fast-page mode to fetch display data quickly into CRT FIFO. When CPU accesses the frame memory, it inserts a CPU cycle via the arbitrating state machine to CPU access.
CRT Controller (CRTC)
The CRT Controller includes a cursor control logic, a horizontal logic, a vertical control logic , and the compatible IBM CRTC registers to generate horizontal synchronous and vertical synchronous signals for external raster-scan CRT monitor. It also provides split-screen capability and smooth scrolling. It generates the blank signals that are sent to RAMDAC (True-color palette DAC) to inhibit pixel display on the screen of monitor.
P.26
It provides a linear memory address logic and a raster address logic to produce memory address signals for fetching display informations from VGA frame memory.
Attribute Controller (ATC)
The Attribute Controller provides flexible high-speed display shifting and attribute processing. It is designed for both text and graphics VGA display applications. In text modes, the Attribute Controller takes in eight bits of character code data and eight bits of attribute data via the Graphics Controller. The character code is used to lookup into a character font table that is located in the Map3 of the display memory. The character font data is loaded into a parallel-to-serial shift register. The serial output from the shift register is used to select a foreground or a background color that is assigned in the attribute data byte. Text blinking, underline and cursor are also the responsibility of the Attribute Controller. In graphic mode, the display data are converted into pixel color data in groups of 16, 8, 2,or 1 adjacent bits, passed through an internal color palette table, and sent out serially to the RAMDAC. In the 256-color mode, the display data is latched twice to form an 8-bit pixel data.
Graphics Controller (GFXC)
The Graphics Controller is the interface between CRT FIFO and both the Attribute Controller during active display and the system microprocessor during display memory reads or writes. During display, memory data is latched from CRT FIFO and sent to the Attribute Controller. In graphic mode, the parallel memory data is converted to serial bit-plane data before being sent out. In text mode, the parallel attribute data is sent to Attribute Controller directly. During a system microprocessor writes or reads to display memory, the graphics controller can perform logical operations on the memory data before it reaches display memory or the system microprocessor data bus, respectively. These logical operations consisted of four logical write modes and two logical read modes.
Address Multiplexer (AMUX)
The Address Multiplexer controls the address bus that is sent to the display memory. It includes RAS* , CAS* , WE* , and OE* timing. During the CRT cycle it sent the display memory address that comes from CRT Controller to the display memory for fetching the display information. When a system microprocessor writes or reads the display memory, the Address Multiplexer connects the system microprocessor address bus to the display memory. When the write buffer function is enabled, a system microprocessor write operation is done first to the Write Buffer logic, then the system address and data signals are latched in the logic. The Sequencer Controller inserts a CPU cycle to perform a write operation by a request coming from Write Buffer logic. At this time, the Address Multiplexer logic connects the address latched by Write Buffer to display memory.
P.27
CRT FIFO (Display FIFO)
The CRT FIFO logic is the interface between display memory and the Graphics controller during the CRT cycle. The Sequencer Controller takes an arbitration between CRT, CPU and Refresh cycle. Because the CRT cycle has the highest priority, the Sequencer Controller can perform a vast fast-page mode to fetch the display data and latch those data into the CRT FIFO. During display , the Graphics Controller takes the display data from the CRT FIFO by the display sequence. Two threshold registers is defined as a high and a low indicator of the CRT FIFO. These registers data are then compared with the number of available display data in the CRT FIFO. The compare outputs are sent to the Sequencer Controller for arbitrating operation. When the contents in the CRT FIFO are under the low threshold, the CRT FIFO issues a request to the Sequencer Controller for more CRT cycles. When the contents in the CRT FIFO leaps over the high threshold or reaches full of the FIFO, the CPU gains the highest priority. With this CRT FIFO logic, the TP6508 optimizes system performance.
Attribute FIFO
The dynamic memory cycle allocation architecture is used in TP6508. Specially , in text mode we integrate 12 levels attribute FIFO storing the attribute information latches the text attribute , ASCII data and cursor state in order to improve performance. The Attribute FIFO logic is the interface between display memory and CRT FIFO during the CRT attribute-accessed cycle in text mode. Two threshold registers is defined as a high and a low indicator of the Attribute FIFO, these registers data compare with the number of available text attribute data in the Attribute FIFO. The content-data are sent to CRT FIFO for arbitrating operation. With the Attribute FIFO logic, the TP6508 optimizes system performance in text mode only .
Write Buffer
When the write buffer function is enabled, a system microprocessor writes to the Write Buffer logic instead of writing directly to the display memory or accessing I/O-write command. A four-stage buffer latches the address, data and other status and maintains a zero wait state write cycle to improve the system performance. If the content of the buffer is not empty, the Write Buffer logic requests the Sequencer Controller to insert a CPU cycle. For compatibility issue, when the content of the buffer is not empty, the Sequencer Controller holds attempts to read display memory and write I/O register until the TP6508 completes processing all items in the Write Buffer logic.
Dual Frequency Synthesizer
The Dual frequency Synthesizer generates the memory clock (MCLK) and the display clock (VCLK) from a single reference frequency - 14.318MHz . . The frequency of each clock is programmable by setting divisor value in the extended regs. that contains field for PLL (Phase Lock Loop), VOC (VoltP.28
age Controlled Oscillator and Post divide control. The PLL parameters for dot /pixel clock (VCLK) are programed VCLK0 or VCLK1 set regs. in SREG C3,C4,C5,C6 and for memory clock (MCLK) are programmed MCLK set regs. in SREG C9,CA. These registers uses to be in conjunction with Denominator and Post Scalar Value Register, is used to determine the frequency of VGA dot clock. These 7 bits numerator (N), 7 bits denominator (D), and 1 bit post scalar (P), for each clock (MCLK or VCLK) determines its frequency according to the following expression: OSC x [N+1] x [2P+2] . MCLK, VCLK(MHz) = [D+1] OSC = reference frequency / 14.318 MHz The reference frequency can be generated with an internal crystal controlled oscillator. Alternatively, it can be supplied from an external TTL source by XTAL1 Pin input. A optional feature is implemented that directs TP6508 to provide the memory clock and the display clock from MCLK and VCLK pin.
True-Color Palette DAC (TDAC)
The True-Color Palette DAC block contains the true color Palettes and three 6-bit or 8-bit digital-to-analog converters. It contains three 256x8 color LUT RAMs for all color mode with the capability to display up to 16.8 million colors simultaneously in both RGB and BGR HiCOLOR-24TM formats. It also support both the popular HiCOLOR-15TM format which uses 5 bits/primary color and the HiCOLOR-16TM color format which uses 5 bits for red , 6 bits for the green , and 5 bit for the blue primary color. The total colors available using the HiCOLOR-15TM format are 32768 while the HiCOLOR-16TM format provides 65536 colors. When the True-Color (16.8M) and Hi-Color (32k/64k) mode isn't activated , it behaves exactly as Pseudo Color format compatible RAMDAC. The color palette, with 256x18-bit entries, converts a color code that specifies the color of pixel into three 6-bit values, one each for red, green, and blue. It also provides a Monitor Sense logic to output a signal to Input Status #0 Register for determining the presence of the CRT monitor. This output is a logical 0 if one or more of the Red, Green, Blue outputs have exceeded the internal voltage reference level by being connected a loaded or unloaded RGB line. After the VGA BIOS programed the palettes and determined the color/mono or no CRT monitor, we can disable the Monitor Sense logic for saving power consumption.
Graphics Engine Controller (GEC)
The Graphics Engine controller generates the control signals for BITBLT (screen-to-screen, hostto-screen) , Color Expansion (1-bit-per-pixel , font-painting) , Line Drawing , Rectangular Clipping , Rectangular Fill, Pattern Fill, Transparence, and Raster operations. They are specifically designed to speed up applications running under GUI environments such as Windows 3.x , Windows applications , X-windows , Autocad , and other CAD/CAM packages. It maintains memory address to locate data in display memory and combines the Source data
P.29
,Destination data ,and Pattern data to perform writing the result back to the destination area under the control of parameters programmed into the chip. The Destination data and Pattern data must reside in the display memory. The Source data and Color expansion pixel data may reside in display memory or be supplied by the CPU during a graphics accelerated operation. Optionally, we support the base addressing and the memory map I/O addressing to access those GEC. registers with 16-bit/32-bit data width. It is more convenient to implement the GUI acceleration function in order to improve the software level performance. All of the accelerated functions are integrated by TP6508 for 8-bit , 16-bit , 24-bit color modes. The encoding of these 256 ROPs is 100% compatible with Microsoft Windows driver interface specification. See Appendix C for a list of Raster Operation.
* Line Drawing
The Graphic Engine implement line drawing function based on the Bresenham's Algorithm . It can draw solid line or dash line by programming the line drawing pattern registers . In the case of drawing dash line , there is one selection to determine whether to keep background data unchanged (transparence) or using the color in "Background Color Registers" as the background color . The pattern format are one pixel mapped to one bit and the first pixel mapped the MSb of the join 32-bits pattern in registers . For the line drawing pattern , one selection is useful for actual screen display that is only used the lower 8-bits of line drawing pattern and one bit mapped four or three pixels . When we draw a more vertical line , the GEC can produce three pixels per mapped bit . When we draw a more horizontal line , the GEC can produce four pixels per mapped bit . Another selection is to determine whether is to draw the last pixel of this drawing line or not .
* Bit Block Transfer
Bit block transfer can copy a rectangular image from a source region to a destination region on display memory with raster operation in 256 ROPs code described in appendix C.
* Color Expansion
Color expansion function can expand monochrome image which one bit represent one pixel to two-color image . All the "1" bits in monochrome image expand to the color in Foreground Color Registers . All the "0" bits expand to the color in Background Color Registers or keep the background data unchanged if 'Background transparency enable' bit is enabled . A useful case of color expansion is filling text in graphic mode . The monochrome data are the character font bitmap data and transfer to TP6508 by writing to "Host to Display Data Transfer Register" . Some additional notes for 'Color Expansion' need to care is described detail in that description of 'Image Write'.
P.30
* Image Write
Image write can transfer color image from host system memory to display memory . The color image data transfer to TP6508 by writing to "Host to Display Data Transfer Register" . The display pixels order of color image is from left to right and from top to bottom if both 'X direction' bit and 'Y direction' bit are programmed to "0" . Some additional notes for 'Image Write' need to care in programming sequence . The first , if Width-X isn't a double-word alignment number for 'Image Write', we muse add a , two or three dummy bytes to fill the last transfer to a double word at the end of each horizontal line . The second , we usually need to check the 'Command FIFO' status in "Graphics Command FIFO Status Register" at the start of any horizontal line . If one horizontal line needs 32 bytes or less to transfer , then the whole line can be written to TP6508 directly . If one horizontal line needs to transfer more than 32 bytes , it must be done after every 32 bytes have been written to TP6508 that we need to check the 'Command FIFO' status .
* Image Read
Image read can transfer color image from display memory to host system memory . The color image data transfer from TP6508 by reading from "Host to Display Data Transfer Register" . The display pixels order is as same as Image Write . Also , for 'Image Read' the additional cares about 'Image Write' need to take care .
* Rectangular Fill & Pattern Fill
Rectangular fill can fill a any size rectangular region on display memory using the color in "Foreground Color Registers" . Also, the pattern fill can use a 8-pixel by 8-pixel image that is storied on display memory as pattern source to fill a any size rectangular region on display memory if pattern is selected by 'Raster operation'.
* Rectangular Clipping
Rectangular clipping define a rectangular region where the image data can be written or cannot . If rectangular clipping is enabled , all the graphic engine functions including of 'Line Drawing' , 'BitBlt' , 'Color Expansion' , 'Image Write' , 'Image Read' , and 'Rectangular Fill & Pattern Fill' can only write these pixels that inside the clipping region or on the boundary if the 'Rectangular clipping polarity' bit is set to "0" . Any pixel outside the rectangular region would not be changes . A another option , GEC can write those pixels that outside clipping region (not including of on the boundary) if the 'Rectangular clipping polarity' bit is set to "1" .
* Color Transparency
Color transparency function can partition the destination pixels into two groups base on its color information . Pixels transfer through GEC with the same color as the "Transparency Color Registers" can not be modified if 'transparency polarity' bit is "0" . Pixels transfer
P.31
through GEC with the different color as the "Transparency Color Register" can not be modified if 'transparency polarity' bit is "1" . In addition , there is a "Transparency Mask Registers" . If the mask bit is "1" , then the color bit of destination pixel is not used in color compare and passes through . These is a example in enhanced 256 color mode . If "Transparency color Registers" is written hex 36 and "Transparency Mask Registers" is written hex 28 and 'transparency polarity' bit is "0" , the destination pixels with color 16h , 36h , 1Eh or 3Eh would not be modified .
Command FIFO
When the Graphics Engine is in operation , we will transfer the necessary parameters ( X/Y direction ,source/destination select, major movement , foreground/background color, ... etc..) to TP6508 by through the Command FIFO and write a graphics accelerate function command (Bit block transfer , Color expansion , Line drawing , ... etc..) in the last. A eight-stage FIFO latches the command data including of graphics accelerate function command and it's parameters and maintains a zero wait state write cycle to improve the system performance. If the content of the FIFO is full , the Command FIFO logic requests the Sequencer Controller to assert the wait cycle until to the FIFO isn't full. A better recommendation was to monitor the 'Graphics Command Status Register' in the group of Graphics Engine Control Register before you write graphics engine command to TP6508.
Hardware Cursor Controller
The Hardware cursor controller supports a 32x32 or 64x64 hardware cursor in 256-color,32k/ 64k-color and 16.8M-color graphics mode. It supports the two-bit plane cursor data structure which provides two colors plus Transparent and Inverted background color by following the Microsoft Windows driver interface specification. In addition, a Auxiliary Color data function can replace the Inverted background color function optionally . The pattern's data format of any pixel (two-bit) is :
Data bit-1 0 0 1 1 Data bit-0 0 1 0 1 Definition Hardware cursor Primary color Hardware cursor Secondary color Transparent Inversion or hardware cursor auxiliary color (decided by GAREG 2A bit-15 selection)
Usually , the cursor pattern is stored in the off-screen display memory . The structure of cursor pattern is 16-bytes by 64-line . All the 16-bytes join together from low address to high address and from LSb to MSb to form a 64x2-bit bit-string . The screen display order of cursor pattern from left to right is mapped to bit string from LSb to MSb per two-bits . To write the cursor pattern to display memory can use Image Write or VGA memory write access directly . The cursor pattern start must address at boundary of double-word . Hardware cursor screen position, type, color selection, and pattern address of the cursor are to be controlled by programming these registers in the group of Graphics engine control registers. The hardware cursor data are allowed of multiple patterns to be storied in display memory and rapidly to be selected one of the patterns as the active cursor's pattern by application program.
P.32
The hardware cursor replaces the software mouse cursor and eliminates to store and restore the screen data as changed the mouse position. Typically, the application software initializes the cursor once and only needs to update the screen position by setting registers. So we can provide a smoothmoving mouse pointer by compared with a software mouse.
PC Video Controller
TP6508 allows up to 24-bit of external RGB video data to be input and merged with the internal VGA data stream. The TP6508 can support two forms of video window: 1) color key input and 2) XY window keying. The X-Y window key input can be used to position the live video window coordinates.
LCD Line Buffer
For dual-scan STN LCD panels, those panels require the upper and lower panels to refresh simultaneously so that we need additional buffer and logic to implement. The additional buffer is called "LCD frame buffer" storing the STN LCD's refresh data which are half of a whole LCD panel's. In TP6508 we have three frame-buffer technique; shadow frame buffer, external frame buffer, pseudo frame buffer, to accelerate LCD display refresh. For shadow frame buffer, we can share the off-screen display memory as the LCD frame buffer by programming the upper display memory region. TP6508 also implements a LCD Line buffer to process and store a line of the LCD refresh data at the start of every CRT horizontal raster. The operation sequence of LCD line buffer is executed by the following steps: 1. Read a line of LCD frame data which are used for the present display frame from shadow frame buffer during the horizontal blank cycle. 2. Write a line of LCD frame data which are used for the next display frame to shadow frame buffer by following the step-1 during the horizontal blank cycle. 3. Output to panel controller from LCD line buffer, a set of frame information of pixels which are read from shadow frame buffer are used to display one of the half LCD panel. 4. Generate and store into LCD line buffer from panel controller, a set of the frame information of pixels which will write to shadow frame buffer are used to display another of the half LCD panel for next frame. 5. Continuously, process the step-3 and step-4 until ending a line of LCD frame data during the horizontal display period. 6. Restart from step-1 for next horizontal raster display and repeat for whole frame display refresh. VGA has the memory bandwidth limitation, but CRT refresh rate higher than memory fetch speed. By external frame buffer technique, we can add another external 256Kx16-bit DRAM-C as a LCD frame buffer. The video-in and pin[8:15] of Panel is also by DRAM-C interface. In addition, the another solution for dual-scan STN LCD panel display is used the pseudo frame buffer technique. It is no additional memory required, but it gets rather lower LCD display contrast than others. It is designed to optimize cost and quality trade-off considerations.
P.33
Panel Controller
The Panel Controller redefines data format from Attribute Controller in LCD/PLASMA/EL display modes. The TP6508 can directly drive various flat panels, including dual-scan/single-scan monochrome, color STN, and color TFT. For monochrome LCD/PLASMA/EL panels, it converts FP0-FP7 to gray level and goes through a special functional operation, sum_to_gray, which is called Gray Scaling. For color LCD panels, it converts FP0-FP23 to R.G.B. color level and goes through two special functional operation, which are called Dithering and Amplitude modulation . The VGA standard defines how colors are mapped to 64 gray scale values on monochrome monitors. The mapping is based on the following weighting equation: I=0.30R+ 0.59G+ 0.11B This formula follows the NTSC conversion standard and is confirmed to display the original color information. Basically, monochrome flat panels do not actually show shades of gray, but only black and white. To build a gray scale, some pixels stay white proportionally longer than they are dark, depending on the shade of gray being built up. Gray scaling ( pattern modulation ) techniques determine which pixels are white or dark for corresponding gray level. If not done well, "Flicker" and "ripples" will occur. Others, the gray scaling techniques also can be using for color flat panel display. Of course it will be occurred on color STN LCD panels that those problems are talking in previous paragraph. The TP6508 controller support both 8 and 16 bit interfaces to STN panels; 9-bit /12-bit/15-bit or 18-bit/ 24-bit interface TFT color LCD panels. In addition, 65536 simultaneous colors are supported for color STN LCD panels, and up to 226,981 visual colors are supported by color dithering techniques. For color TFT LCD panels, TP6508 can support 16.8M simultaneous colors on 24-bit interface. Further more, 512 simultaneous colors are supported for 9-bit interface color TFT LCD panels, and up to 185,193 visual colors are supported by amplitude modulation techniques. To avoid flicker and ripple phenomenon. There are three approaches: (1) increase frame rate: The higher the switching rate, the better the display quality. (2) adequate modulation sequences: Spread pixels frame ON time on continuous "timing". (3) dispersion modulation: Enhance modulation task from time spreading to spatial spreading each pixel on/off ratio does not change, but has "time shift for neighboring pixels.
P.34
* Gray Scaling
Gray scaling is the continuous frame ON/OFF ratio according to the corresponding gray level. We can do 2/4 gray level for pixels as follow:
FRAME 0
FRAME 1
FRAME 2
FRAME 3
But notice how the dark pixels line up in diagonal columns. These rows of diagonal columns create regular striations marching across the gray region cycle by cycle. Alternating the pixels other ways doesn't solve the problem but only creates vertical or other diagonal columns. If not designed correctly, a controller will exhibit diagonal columns jitter or scrambled movement across gray regions, greatly degrading display quality. How to eliminate the stripping wave become the key point of the panel VGA design. Basically, manufactures obey the following rules: (1) Pixels On/Off ratio are proportional to gray level. (2) The modulation sequence of neighboring pixels are uncorrelative to reduce stippling wave.
Frame Seq.
0
0 1
1 0 0 0 0
2 0 1 1 1
3 1 0 0 0
4 0 0 0 1
5 1 1 1 0
6 0 0 0 0
7 0 0 1 1
S 3/8 S 3/8 S 3/8 S 3/8
2 3
0
1
S 3/8 1 S 3/8 1 S 3/8 0 S 3/8 0
3 2
NOTE : 1 = ON , 0 = OFF
P.35
We can see the following situation:
0
1
2
3
4
5
6
SP508B06.GEM 85/02/12
7
L.R.Y.
According to the above rules, we can see the ambiguous stippling wave. It is clear that we find a method to eliminate wave phenomenon. But now another problem appear, how to find the best modulation sequence for all gray levels, so the adequate trade-off are needed.
* Maximum Contrast and Attribute Emulation
When color text converts to mono LCD panel mode, remapping gray levels between foreground and background are probably to the same gray level. It is difficult to recognize text forms on the screen. We provide user 'maximum contrast' option to enhance LCD display contrast. The operation as following:
P0-P7
GRAY PALLETE
I0-I5
M FORE BACK CG
(G,R,B,I) (G,R,B,I) ATTRIBUTE REMAPPING P/S SEL SYNC. DELAY
TO GRAY SCALING
U X
MAXIMUM CONTRAST
SP508B09.GEM 85/02/12 L.R.Y.
When foreground attribute (G0,R0,B0,I0) is larger than background attribute (G1,R1,B1,I1), we set (G0,R0,B0,I0) = (1,1,1,1) = 63 gray level, (G1,R1,B1,I1) = (0,0,0,0) = 0 gray level.When (G0,R0,B0,I0) = (G1,R1,B1,I1), we reverse the original attribute gray level. There is another option called attribute emulation. The user enable the 'attribute emulation' function. Attribute Remapping does eight clear contrast automatically, so user can get the best looking in the text mode.
P.36
* Frame Buffer
For dual-scan STN LCD panel , we must use "acceleration mode ". We can use the shadow frame buffer technique to fixed it . In the others, VGA has the memory bandwidth limitation , but CRT refresh rate higher than memory fetch speed. How to solve this series problem , we can add another external 256Kx16-bit DRAM as a LCD frame buffer.
External Frame Buffer
Frame Buffer DRAMs
Shadow Frame Buffer
DRAMs Frame Buffer
VGA
Display Buffer
VGA
Display Buffer
A B C D E... 1 2 3 4 5... SCREEN
12345 Start Frame ABCDE Start Frame
A' 2 3 4 5 R:1 W:A' 1' B C D E R:A W:1'
A' B' 3 4 5 R:2 W:B' 1' 2' C D E R:B W:2'
........ ........
A' B' C' D' E' End Frame 1' 2' 3' 4' 5' End Frame
SP508B08.GEM
85/02/12
L.R.Y.
When VGA scans upper panel, frame buffer stores the pixel data of lower panel . Every pixel needs only one bit to present on/off information . We provide following figures to show operating procedure: Left diagram appears actual screen circumstance . A,B,C,D.. AND 1,2,3,4 are the continuous pixels of upper/lower panel. Right rectangles present the interior data of screen buffer . VGA does read-modify-write to the frame buffer consecutively . Upper buffer presents continuous process of scanning VGA upper panel, so does lower panel .
* Color Dithering
For color STN LCD panel , TP6508 can add visual colors by color dithering techniques . The dithering technique uses a group of dithering pattern in 4 by 4 pixel-block and gray modulation to generate the gray shades for each of R,G,B . The dithering patterns for each shades is designed so that it creates minimum flicker and stripping wave on the panel screen. In the extended indexed register CREG A9 , we can select the various dither algorithm and types to increase colors of the panels .
* Amplitude Modulation
For color TFT LCD panel, TP6508 can add visual colors except the 24-bit true color panel by
P.37
color amplitude modulation techniques. The red, green, blue color data that directly come from the palette RAM provide the code for each color. The amplitude modulation technique uses a group of weighting codes and frame (time) modulation to generate the shading information for each of R,G,B. In the extended indexed register CREG A8 , we can select the various amplitude modulation types to increase colors of the panels .
* Display Combination
The new generation of LCD VGA provides a simultaneous CRT/LCD or CRT/PLASMA display function . This adds a new dimension to the promotional application of portable computers by offering a more versatile visual demonstration . TP6508 also provides this function to extend added value to portable computer. In order to accommodate the limited minimum signal width of CRT VGA, the working frequency of the LCD VGA should at least be 6MHz . The TP6508 will provide a Frame Rate of about 120Hz at this working frequency. In spite of the above, the CRT VGA still has its draw backs when used for commercial demonstration because of its limited size . With the arrival of low priced TV's (60" to 120"), why not harness the big TV screen to reproduce the portable computer LCD display? To achieve this function, TP6508 has integrated the TV interface synchronization signal circuit . It needs only one analog IC to externally convert the RGB and synchronization signal to RS-170 standard signal for TV . The RS-170 signal is then transmitted through AV terminal to TV . TP6508 has overcome the technical problem of interlaced scan on LCD . This makes the simultaneous display of TV/LCD come true. Presently, TP6508 supports NTSC and PAL TV standard. The SECOM standard support will be available in the future.
* TV Interface
The simultaneous display on both TV and LCD panel is rather an unique design of TP6508. There are many add-on cards or devices on the market which can convert VGA signal to TV display signal, but they can not accomplish a simultaneous display on LCD . The reason is that it is not as easy to perform a interlaced scan on LCD as on CRT . This problem has to be resolved from the internal logic design of VGA. On the other hand, TP6508 can generate synchronization signal that completely matches with the standard of RS-170. With an external NTSC encoder (A example , MC1377 , is set in Application Circuit chapter) , TP6508 can transmit image to TV through A/V terminal . In order to preclude flickering on TV display, TP6508 uses a non-interlaced scan to stabilize the Frame Rate at 60Hz . Under this Frame Rate, all display modes of IBM VGA are supported. The optimum resolution is 640x480 with 256 colors. Under TV display mode, the HSYNC signal which is originally sent to VGA are converted to composite sync signal . This composite signal combines the horizontal sync, vertical sync and the equalization pulse . It is necessary of the 3.58 MHz crystal to generate a reference frequency for color burst signal. This frequency is used as the color calibration signal if adjusted by variable capacitor . Due to the limitation of TV's resolution and Frame Rate, the displayed image may not be as good as that of VGA display, but its display of big fonts and graphics as in a commercial demonstration and presentation, is distinctively sharp .
P.38
Power Management Controller (P.M.C.)
The TP6508 has a special function which is a power management unit to generate the power control signals for Dual frequency synthesizer , RAMDAC, other block devices of TP6508, and Montor output timing . It's implemented with the VESA DPMS(Display Power Management Signaling) standard and designed to provide power management for Green PC systems . The TP6508 provides trigger pins and timers to determine when the system is idle . When idle, the TP6508 can remove power from unused internal block devices . The TP6508 also supports slow refresh DRAM for power saving. The TP6508 has four main operating modes: Active mode, Standby mode , Suspend mode , and Off mode. The I/O read/write ( register programming/keyboard request ) , external trigger pins, and the time-out control the transition between each mode . TP6508 supports one external trigger pins , OFF pin .
DPMS States:
State On(Active) Standby Suspend Off Cover-Close HSYNC Pulses No Pulses Pulses No Pulses Pulses VSYNC Pulses Pulses No Pulses No Pulses Pulses CRT Active Blanked Blanked Blanked Active Flat Panel Active Blanked Blanked Blanked Blanked Power Saving None Minimal Substantial Maximum Minimal
* DPMS Operating Modes: 1. On(Active) Mode
This is the start-up or wake-up mode of the system. The CPU is operating at maximum speed . Fixed disks and floppy are working with normal situation and the VGA is active normal .
2. Standby Mode
Standby mode is the first power saving mode . The standby mode is entered from the active mode when the time specified by the P.M.C. time-out register, or user I/O register programming . Resume may be initiated by I/O register programming, or keyboard request . There are no CRT cycle on in this mode and turns off internal DAC . But video memory and register access allowed.
3. Suspend Mode
Suspend mode is the lower power saving mode . It is as same as the standby mode to TP6508's internal power saver except the output of HSYNC and VSYNC signal for various power saving mode monitor by VESA DMPS standard. The different display sync output between Standy mode and Suspend mode is descripted on previous 'DMPS States' table . Suspend may be initiated by the P.M.C. time-out register, or user I/O register programming . Resume may be initiated by I/O register programming , keyboard request.
4. Off Mode
P.39
Off mode is the lowest power mode . It may be initiated by the P.M.C. time-out register, user I/O register programming or OFF/SUSPEND pin input . Resume may be initiated by the OFF pin external trigger input. In this mode, system will turn off CPU cycle, CRT cycle, screen buffer, display signal, internal dual frequency synthesizer and internal DAC , meanwhile, does DRAMs slow refresh. Display memory and register accessing isn't allowed .
5. COVER-CLOSE MODE
Cover-close mode is the special power mode using for laptop PC. or Notebook PC. system on closing the machine-cover . Specially, this mode replace OFF mode when the user programmed the extended register 3c4/3c5 index D2h bit 7 to logical 1 . It may be initiated by the OFF pin. Resume may be initiated by external trigger input . In cover-close mode, system will turn off panel backlight, and down saving internal partial panel block device power . Then the CRT display is normal.
3->4 2->3 1->2 * I/O Register Programming * I/O Register Programming * I/O Register Programming * Off timer time-out * Suspend timer time-out * Standby timer time-out * OFF pin active
2->1 * Keyboard request * VGA access
3->1 * Keyboard request * VGA access
4->1 * Keyboard request * VGA access * OFF pin not active
STANDBY
ON
2
SUSPEND
1
COVER-CLOSE
3 5 4
OFF
P.40
* Flat Panel Power sequencing
The TP6508's power supply management design is very flexible . The following Figure shows the timing diagram and the control signals related to power supply management . It is a very helpful reference for VGA designing with portable or notebook computers . It is worth mentioning that the FPVCC, FPVEE, and FPBACK signals can effectively resolve problems of LCD power sequencing . The FPVCC signal is used to turn On/OFF the digital power(+5 Volt) for the digital logic of the LCD panel . The FPVEE signal is sent to bias voltage generator of the LCD panel driver for control signal ON/OFF application . The FPBACK signal can be sent to the back-light voltage generator to administer ON/OFF control . There must be a 64ms skew between the FPVCC's and FPVEE's timing during power on(into On mode) sequence and be a 16ms skew during power off (into Standby/Suspend/Off/Cover-Close mode) sequence . The sequence is reversed between Power On and Power Off. For the convenience of design, the length of skew is fixed and not adjustable, but Topro is confident that this skew will satisfy the requirement of most panels .
FPVCC
LCD Digital Logic Power
64ms
16ms
Signals
Tri-state Tri-state
64ms
16ms
FPVEE
LCD Driver Power
FPBACK
LCD Backlight Power
LCD Panel Power Sequencing
SP508B11.GEM 85/02/12 L.R.Y.
P.41
VII. Registers
TP6508 contain seven groups of registers . These are IBM Standard Register Backward Compatible Register , Extended Sequencer Register , Extended CRTC Register , Panel Control Register , PCI Local Bus Configuration Register, Graphics Engine Register.
IBM Standard Register
There are five sets of registers in the video subsystem. All but the system microprocessor data latches and the attribute address flip-flop are readable. The following figure lists the registers and the I/O address where they are located. The figure also lists whether or not they are read/write, read-only, or write-only.
* General Registers Misc. Output Register ( MISCREG: R/3CCH, W/3C2H )
D0 D1 D2 D3 D4 D5 D6 D7 I/O address select ( 0/3BXH, 1/3DXH ) Enable video RAM ( active high, no effect on display refresh ) Clock select 0 ( 00/25MHz, 01/28MHz ) Clock selcet 1 ( 10/auxi., 11/45MHz ) Reserved Odd/Even page select ( for diagonostic use ) Horizontal sync. polarity select ( 0/positive, 1/negative) Vertical sync. polarity select ( 0/positive, 1/negative)
Input Status Register 0 ( INSTREG0 : R/3C2H )
D0-3 D4 D5-6 D7 Reserved Switch sense bit (match with clock select 0/1 ) Reserved (0) CRT interrupt ( 0/cleared, 1/pending )
Input Status Register 1 ( INSTREG1 : R/3?AH )
D0 D1-2 D3 D4 D5 D6-7 Display enable ( active low ) Reserved Vertical retrace (VGA) /CG out (Herculus) Color plane register check 0 ( P0, P4, P1, P6 ) Color plane register check 1 ( P2, P5, P3, P7 ) Reserved
Feature Control registe ( FEATREG: R/3CAH, W/3?AH )
D0-7 Reserved
VGA DAC I/O Ports
3C6H 3C7H 3C7H 3C8H 3C9H Pixel mask register DAC state register ( read only, VGA support D0-D1 ) Look-up table read index ( write only, RAMDAC support ) Look-up table write index Look-up table data register
P.42
* Sequencer Registers Sequencer Address Register ( SEQIDREG : RW/3C4H )
D0-7 SEQUENTIAL ADDRESS BITS (00-FF)
Reset Register ( SR00 : RW/3C5H )
D0 D1 D2-7 Asynchrous reset ( active low ) Synchrous reset ( active low ) Reserved
Clocking Mode Register ( SR01 : RW/3C5H )
D0 D1 D2 D3 D4 D5 D6-7 8/9 dot clocks select ( 0/9, 1/8 ) Reserved Shift load ( 0/normal, 1/divide 2 ) Dot clock ( 0/normal, 1/divide 2 ) Shift 4 ( 0/D2, 1/divide 4 ) Screen off ( active high ) Reserved
Map Mask Register ( SR02 : RW/3C5H )
D0-3 D4-7 Enable map 0-3 ( active high ) Reserved
Character Map Select Register ( SR03 : RW/3C5H )
D0 D1 D2 D3 D4 D5 D6 Character Character Character Character Character Character Reserved generator generator generator generator generator generator table table table table table table select select select select select select B B A A B (MSB) A (MSB)
Memory Mode Register ( SR04 : RW/3C5H )
D0 D1 D2 D3 D4-7 Reserved Extended memory ( 0/64k, 1/256k ) Odd/Even ( active low ) Chain 4 ( 256 colors only, active high ) Reserved
* CRT Registers CRT Address Register ( CRTIDREG : RW/3?4H )
D0-4 D5-7 Sequential address bits Reserved
Horizontal Total Register ( CR00 : RW/3?5H )
D0-7 Horizontal total ( -5 )
Horizontal Display Enable End Register ( CR01 : RW/3?5H )
D0-7 Horizontal display enable end ( -1 ) P.43
Start Horizontal Blanking Register ( CR02 : RW/3?5H )
D0-7 Start Horizontal Blanking ( -1 )
End Horizontal Blanking Register ( CR03 : RW/3?5H )
D0-4 D5-6 D7 End horizontal blanking bit 0-4 Display enable skew bit 0-1 Test (1)
Start Horizontal Retrace Pulse Register ( CR04 : RW/3?5H )
D0-7 Start horizontal retrace pulse bit 0-7
End Horizontal Retrace Register ( CR05 : RW/3?5H )
D0-4 D5-6 D7 End horizontal retrace bit 0-4 Horizontal retrace skew bit 0-1 End horizontal blanking bit 5
Vertecal Total Register ( CR06 : RW/3?5H )
D0-7 Veratical Total bit 0-7 ( -2 )
CRTC Overflow Register ( CR07 : RW/3?5H )
D0 D1 D2 D3 D4 D5 D6 D7 Vertical total bit 8 Vertical display enable end bit 8 Vertical retrace start bit 8 Start vertical blank bit 8 Line compare bit 8 Vertical total bit 9 Vertical display enable end bit 9 Vertical retrace start bit 9
Preset Row Scan Register ( CR08 : RW/3?5H )
D0-4 D5-6 D7 Preset row scan ( pexil scrolling ) Byte panning control bit 0-1 Reserved
Maximum Scan Line Register ( CR09 : RW/3?5H )
D0-4 D5 D6 D7 Maximum scan line bit 0-4 Start vertical blank bit 9 Line compare bit 9 200-->400 line conversion
Cursor Start Register ( CR0A : RW/3?5H )
D0-4 D5 D6-7 Row Scan cursor start bit 0-4 Cursor off ( active high ) Reserved
Cursor End Register ( CR0B : RW/3?5H)
D0-4 D5-6 D7 Row Scan cursor end bit 0-4 Cursor skew bit 0-1 Reserved
P.44
Start Address High Register ( CR0C : RW/3?5H )
D0-7 High order start address bit 0-7
Start Address Low Register ( CR0D : RW/3?5H )
D0-7 Low order start address bit 0-7
Cursor Location High Register ( CR0E : RW/3?5H )
D0-7 High order cursor location bit 0-7
Cursor Location Low Register ( CR0F : RW/3?5H )
D0-7 Low order cursor location bit 0-7
Vertical Retrace Start Register ( CR10 : RW/3?5H )
D0-7 Low order vertical start bit 0-7 ( 10 bits total )
Vertical Retrace End Register ( CR11 : RW/3?5H )
D0-3 D4 D5 D6 D7 Vert. retrace end bit 0-3 Clear vert. interrupt Enable vert. interrupt Select refresh cycles ( 0/3 cycle, 1/5 cycle ) Protect CR00-CR07
Vertical Display Enable End Register ( CR12 : RW/3?5H )
D0-7 Low order vert. display enable end bit 0-7 ( -1 ) ( 10 bit total )
Offset Register ( CR13 : RW/3?5H )
D0-7 Logical line width of the screen bit 0-7
Underline Location Register (CR14 : RW/3?5H )
D0-4 D5 D6 D7 Underline location bit 0-4 Count by 4 Doubleword Mode Reserved
Start Vertical Blanking Register ( CR15 : RW/3?5H )
D0-7 Low order vertical blanking bit 0-7 (-1) ( 10 bits total )
End Vertical Blanking Register ( CR16 : RW/3?5H )
D0-7 End vertical blanking bit 0-7
CRT Mode Control Register ( CR17 : RW/3?5H )
D0 D1 D2 D3 D4 D5 D6 D7 RA0 replace MA13 ( active low ) RA1 replace MA14 ( active low ) Hor.retrace select ( 0/normal, 1/double scan ) Memory address count by 2 ( 0/byte refresh, 1/word refresh ) Reserved Address wrape ( 0/MA13:64k, 1/MA15: 256k ) Word/Byte mode ( 0/normal, 1/MA13 or MA15 replace MA0 ) Hardware reset ( active low , reset VR and HR )
P.45
Line Compare Register ( CR18 : RW/3?5H)
D0-7 Low order compare line number bit 0-7 ( 10 bits total )
* Graphics Registe Graphics address Register ( GFXIDREG : RW/3CEH )
D0-4 D5-7 Graphics address bit 0-4 Reserved
Set/Reset Register ( GR00 : RW/3CFH )
D0-3 D4-7 Set/Reset map bit 0-3 Reserved
Enable Set/Reset Register ( GR01 : RW/3CFH )
D0-3 D4-7 Enable Set/Reset map bit 0-3 Reserved
Color Compare Register ( GR02 : RW/3CFH )
D0-3 D4-7 Colore Compare map bit 0-3 Reserved
Data Rotate Register ( GR03 : RW/3CFH )
D0-2 D3 D4 D5-7 Rotate count bit 0-2 Function select bit 0 ( 00/unmodified, 01/ANDed ) Function select bit 1 ( 10/ORed, 11/XORed ) Reserved
Read Map Select Register ( GR04 : RW/3CFH )
D0 D1 D2-7 Map select bit 0 ( 00/Map 0 , 01/Map 1 ) Map select bit 1 ( 10/Map 2 , 11/Map 3 ) Reserved
Graphics Mode Register ( GR05 : RW/3CFH )
D0 D1 D2 D3 D4 D5 D6 D7 Write mode bit 0 ( 00/dirct write, 01/latch write ) Write mode bit 1 ( 10/packed write, 11/SR write ) Reserved Read type ( 0/map select read, 1/color compare read ) Odd/Even ( active high, for Text mode ) Shift register ode ( for CGA mode 4,5 ) 256 color mode ( active high ) Reserved
Graphics Misc. Register ( GR06 : RW/3CFH )
D0 D1 D2 D3 D4-7 Graphics enable ( active high ) Chain odd and even maps Memory address select ( 00/A0000-BFFFF, 01/A0000-AFFFF ) Memory address select ( 10/B0000-B7FFF, 11/B8000-BFFFF ) Reserved
P.46
Color Don't Care Register ( GR07 : RW/3CFH )
D0-3 D4-7 Plan 0-3 Color Don't care Reserved
Bit Mask Register ( GR08 : RW/3CFH )
D0-7 Mask data bit 0-7
* Attribute Registers Attribute Address Register ( ATRIDREG : RW/3C0H )
D0-4 D5 D6-7 Graphics address bit 0-4 Palette address source ( 0/CPU, 1/CRTC ) Reserved
Pallete Register ( AR00-AR0F : R/3C1H, W/3C0H )
D0-5 D6-7 P0-5 Reserved
Attribute Mode Control Register ( AR10 : R/3C1H, W/3C0H )
D0 D1 D2 D3 D4 D5 D6 D7 Graphics/Text mode select ( 0/text, 1/graphics ) Color/mono emulation ( 0/color , 1/mono ) Enable line graphics characters ( ACSII C0-DF, active high ) Attribute code ( 0/select ackground, 1/enable blink ) Reserved PEL panning compatiblity with the line compare ( active high ) PEL width ( 0/normal, 1/256 colors ) P5/p4 select source ( 0/normal, 1/color select reg. )
Over-scan Color Register ( AR11 : R/3C1H, W/3C0H )
D0-7 Over scan color bit 0-7
Color Plan Enable Register ( AR12 : R/3C1H, W/3C0H )
D0-3 D4 D5 D6-7 Enable plan 0-3 Video status MUX bit 0 ( 00/P2-P0, 01/P5-P4 ) Videl status MUX bit 1 ( 10/P3-P1, 11/P7-P6 ) Reserved
Horizontal PEL Panning Register ( AR13 : R/3C1H, W/3C0H )
D0 D4-7 Horizontal PEL panning bit 0-3 Reserved
Color Select Register ( AR14 : R/3C1H, W/3C0H )
D0-3 D4-7 Select color 4-7 Reserved
P.47
Backward Compatible Register Description
The following registers are TP6508 backward compatible registers. These registers are accessed by first writing the index of the desired register to the Sequencer Index register, i.e. address Hex 3C4 and then accessing the register using the address Hex 3C5. Specially , these are not protected by password/Identification register (Extended Index Register Hex 05) .
Extended Indexed Register CREG 05 : Password/Identification Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
Write operation (=> Hex 86) : D0-7 Password Read operation (=> Hex 0B for correct password or Hex F4 for incorrect passward): D0-4 Identification Code D5-7 Chip Version Code
With the password register, the TP6508 protects the extended register to avoid incorrectly application programming. When user wants to access the extended registers, he must first write Hex 86 to this register to unlock the protection. When user reads the content of this register, he can get a value of Hex 0B that is used to distinguish the TP6508. To enable the protection operation by writing other values into the register , and you can read back a value of Hex F4.
Extended Indexed Register SREG 06 : Extended Memory Bank MISC. Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3-7
Bit 0
Enable Bank C and Bank D Disable dual Bank (window) operation for Bank C and D Enable read/write bank operation Reserved
For compatibility with the HM86305 that has only three bit bank select for up to 512K- byte display memory, a logical 0 directs the bank selection from Bank A , Bank B or both. When this bit is set to a logical 1, the TP6508 enables both Bank C & D and Bank A & B. Refer the SREG 09 bit 0-5 description. This bit is used to select the BANK D location address from hex. A0000 to hex. AFFFF or from Hex B0000 to Hex BFFFF . A logical 0 selects BANK D addressing in hex. B0000 to hex. BFFFF. A logical 1 forces BANK C in write access operation and BANK D in read access operation only. Bank C & D are both location at address hex. A0000 to AFFFF . A logical 0 doesn't enable it. Bit-2 Bit-1 Bit-0 Memory bank & segment selection 0 0 0 BANK A&B R/W access by segment address A000&B000 0 0 1 BANK C&D R/W access by segment address A000&B000 0 1 0 BANK A R/W access by segment address A000 only 0 1 1 BANK C R/W access by segment address A000 only 1 X X BANK C Write access & BANK D Read access by segment address A000 Reserved.
Bit 1
Bit 2
Bit 3-7
P.48
Extended Indexed Register SREG 07 : CPU Start address Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-3 CPU start address bit 0 to 3 D4-7 Reserved
Bit 0-3 These bit are used to set the CPU start address that specifies the offset from original address point to the first byte of BANK 0. It can solve the Bank(Window) boundary problem. The unit size of CPU start address is in 4 KB, so we can adjust the offset address domain from 0 to 60 KB. Reserved.
Bit 4-7
Extended Indexed Register SREG 08 : Extended Memory Bank C Select Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-4 Memory bank C select bit 0 to 4 D5-7 Reserved
Bit 0-4 When the TP6508 is configured with over 512k-byte display memory, a segment memory i.e. , 64Kbyte, only access a small part of the display region. These bits help the user to access the remaining pixel data. When the user wants to move lots of pixel data from one bank to another, the microprocessor suffers from executing I/O write to modify the content of the bank select register. With its dual and overlapping windowsarchitecture, operations performance has improved drastically.Each window is associated with a four-bit bank select register. When the user wants to translate a good deal of pixel data from one bank to another, he can programs two bank registers before translation once instead of the modifying every pixel data movement. These bits are associated with the window down address region from Hex A0000 to Hex AFFFF. Reserved.
Bit 5-7
Extended Indexed Register SREG 09 : Extended Memory Bank D Select Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-4 Memory bank D select bit 0 to 4 D5-7 Reserved
Bit 0-4 These bits perform the same function as with the previous register except that they are associated with the window down address region from Hex B0000 to Hex BFFFF under SREG 06 bit-1 being set to logical 0. When SREG 06 bit-1 is set to logical 1, they are associated with the same address region from Hex A0000 to Hex AFFFF. Reserved.
Bit 5-7
Extended Indexed Register SREG E0,E1,E2 : Scratched Register 1,2,3
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Reserved
P.49
Extended Indexed Register SREG EE : Memory Bank Select Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1-3 D4-6 D7
Dual window operation enable Select Bank B bit 0 to 2 Select Bank A bit 0 to 2 Reserved=1
VGA Subsystem Enable Register
This is a read/write register. Port address is Hex 3C3 or Hex 46E8 selected by VGA Subsystem Enable Port Select control bit that comes from Extended Indexed Reg. Hex CE bit 4. Default value after hardware reset is selected by Extended Indexed Reg. Hex CE bit 5. If this bit is a logical 1 , and then the value is Hex 00 when the port address is Hex 3C3 or is Hex 00 when the port address is Hex 46E8. If this bit is a logical 0 , and then the value is Hex 01 when the port address is Hex 3C3 or is Hex 08 when the port address is Hex 46E8.
D0 D1-2 D3 D4-7
VGA subsystem enable ( for Port Hex 3C3) Reserved VGA subsystem enable ( for Port Hex 46E8) Reserved
P.50
Extended Sequencer Register Description
The following registers are TP6508 extended sequencer registers. These registers are accessed by first writing the index of the desired register to the Sequencer Index register, i.e. address Hex 3C4 and then accessing the register using the address Hex 3C5. These registers are protected by password/Identification register (Extended Index Register Hex 05) .
Extended Indexed Register SREG C0: VGA Control Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2
Enable CPU write buffer Disable VGA palette snooping for VESA local bus Enable linear addressing Enable memory map I/O Enable Graphics engine read/write Graphics engine active enable Enable VAFC interface Enable VAFC PCLK output divided by 2
TP6508 support CPU write buffer to improve the performance when CPU writes a data into video memory . A logical 1 enables this function, a logical 0 disables it. A logical 0 enables TP6508 snoops VGA palette write for VESA local bus . A logical 0 disables it. IBM compatible display address uses low base 1M address bit 0 to 19 and locates at Hex A0000 to AFFFF or Hex B0000 to BFFFF . A logical 1 enables TP6508 to remape display memory in continuously linear address at over the base 1M-byte address . A logical 0 disables it and forces TP6508 in bank memory addressing on enhanced display mode. By base addressing, we can used the reg. SREG F0 and SREG F1 to assign the base low address . (See the reg. description of SREG F0 and SREG F1) Then TP6508 can access these registers with 16-bit data width by decoding at them, being conjunction with 'x..' and 'Y..' , directly. By memory map I/O addressing forces TP6508 uses memory command accessing to access I/O command and remapes I/O command address on where are determined by Memory Mapping I/O Command offset Register ( See the reg. description of SREG D8). Bit 3 Addressing mode 0 Base Addressing 1 Memory I/O Addressing A logical 1 enables to access the Graphics Engine Control registers. A logical 1 enables TP6508's Graphics Engine in operated mode. A logical 0 disables it . A logical 1 enables TP6508 implement VAFC interface. A logical 1 forces TP6508 output PCLK frequency divide by two for VAFC.
Bit 3
Bit Bit Bit Bit
4 5 6 7
Extended Indexed Register SREG C1 : Extended mode select Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4
Enhanced 16 color mode enable Enhanced 256 color mode enable Enable 32k super-colors mode Enable 64k super-colors mode Enhanced 16.8M color enable
P.51
D5 D6 D7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Enable 132 column text mode Enable interlace display Enable bank memory addressing on enhanced 16-color display
A logical 1 directs the TP6508 to work in the enhanced 16 color mode. A logical 1 forces the TP6508 to display the 256 color except the Mode 13. When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to support Hicolor-15 TM compatible display mode architecture by setting this bit to logical 1. When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to support Hicolor-16 TM compatible display mode architecture by setting this bit to logical 1. When bit-1 was set to logical 1, we can force the build-in internal RAMDAC to support Hicolor-24 TM compatible color display mode architecture by setting this bit to logical 1. A logical 1 directs the TP6508 to display 132 columns text mode. A logical 0 directs the TP6508 to perform a non-interlaced display mode. A logical 1 enables a interlaced display mode to fit the synchronous frequency of the monitor. A logical 1 directs TP6508 to display enhanced 16-color mode by bank memory addressing. A logical 0 directs TP6508 to display enhanced 16-color mode by location continuous 128K-byte memory at A0000 to BFFFF.
Extended Indexed Register SREG C2: Clock Select Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4 D5 D6 D7
Bit 0-1
Extended clock select bit 0 to 1 Reserved Enable extended clock select bit 0 and bit 1 ACTI statue/data ACTI Pin(pin 53) output control Select 16.8M color mode in four-byte architecture
When the bit-4 was set to logical 1, these two bits replace the MISCREG bit 2-3. The bit-0 or MISCREG bit-2 is used to select the internal VCLK clock synthesizer programming regs. set for deciding video clock frequency. MISCREG bit-2 or SREG C2 bit-0 Selected Regs. group 0: Use the SREG C3,C5 1: Use the SREG C4,C6 Reserved. A logical 1 directs previous two bits as the video clock select signals. A logical 0 inhibits the function of extended clock select bit 0 and 1. This bit is reflected the ACTI pin status. When ACTI is redefined as user control output that is configured by bit 1, this bit determins the data output on ACTI pin. When SREG D0 bit 6=1,SREG D9 bit 1-0=11, this bit can select ACTI Pin(pin 53) output function as following: Bit 6 ACTI Pin Function 0 ACTI output. ACTI responces high during vaild VGA access operations. 1 User control output. Output data from SREG C2 bit 5. Ture color(16.8M color) display mode memory access architecture selection:
Bit 2-3 Bit 4 Bit 5 Bit 6
Bit 7
Bit 7
0 1
16.8M color mode architecture selection
In three-byte memory architecture. In four-byte memory architecture..
P.52
Extended Indexed Register SREG C3 : VCLK0 Numerator Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 9C.
D0-6 VCLK0 numerator bit 0 to 6 D7 VCLK0 oscillation divider
Bit 0-6 This register,in conjunction with VCLK0 Denominator and Post Scalar Value Register, is used to determine the frequency of video clock. These 7 bits numerator (N), 7 bits denominator (D), and 1 bit post scalar (P), for each clock (VCLK) determines its frequency according to the following expression: OSC x [N+1] x [2P+2] VCLK(MHz) = [D+1] , OSC= 14.318 (MHz) This bit is used to divide the internal generated oscillation frequency. A logical 0 indicates to do it divided by two. A logical 1 indicates to do it divided by four. Normally, we set to logical 1 when VCLK0 outputs frequency lower 50MHz.
Bit 7
Extended Indexed Register SREG C4 : VCLK1 Numerator Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex A8.
D0-6 VCLK1 numerator bit 0 to 6 D7 VCLK1 oscillation divider
Bit 0-6 Bit 7 This register,in conjunction with VCLK1 Denominator and Post Scalar Value Register, is used to determine the frequency of video clock . This bit is used to divide the internal generated oscillation frequency. A logical 0 indicates to do it divided by two. A logical 1 indicates to do it divided by four . Normally, we set to logical 1 when VCLK1 outputs frequency lower 50MHz.
Extended Indexed Register SREG C5 : VCLK0 Denominator and Post Scalar Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 83.
D0 VCLK0 post scalar D1-7 VCLK0 denominator bit 0 to 6
Bit 0-7 This register,in conjunction with VCLK0 Numerator Value Register, is used to determine the frequency of video clock.
Extended Indexed Register SREG C6 : VCLK1 Denominator and Post Scalar Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex A3.
D0 VCLK1 post scalar D1-7 VCLK1 denominator bit 0 to 6
P.53
Bit 0-7
This register,in conjunction with VCLK0 Numerator Value Register, is used to determine the frequency of video clock.
Extended Indexed Register SREG C7 : CRT FIFO Threshold Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-3 CRT FIFO threshold high bit 0 to 2 (default = 0, point to actual value 4) D4-7 CRT FIFO threshold low bit 0 to 2 (default = 0, point to actual value 3)
Bit 0-3 Bit 4-7 In the TP6508, memory cycle allocation is dynamic. When FIFO accumulated data is larger than FIFO threshold high value, CPU cycle can occur without any wait state. When CPU access video memory, it must depend on remainder data of CRT FIFO . When the number of CRT FIFO data is less than the FIFO threshold low value, the only one thing can do is CRT access. Threshold value affects the performance of TP6508.
Extended Indexed Register SREG C8 : Attribute FIFO Threshold Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-2 Attribute FIFO threshold bit 0 to 2 (default = 0, point to actual value 1) D3-7 Reserved
Bit 0-2 Bit 3-7 This dynamic memory cycle allocation architecture is used in TP6508 . Specially, in text mode we integrate the Attribute FIFO storing attribute data in order to improve performance in text mode. Reserved
Extended Indexed Register SREG C9 : MCLK Numerator Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex A1.
D0-6 MCLK numerator bit 0 to 6 D7 MCLK oscillation divider
Bit 0-6 This register,in conjunction with MCLK Denominator and Post Scalar Value Register, is used to determine the frequency of video clock. These 7 bits numerator (N), 7 bits denominator (D), and 1 bit post scalar (P) for clock (MCLK) determines its frequency according to the following expression: OSC x [N+1] x [2P+2] MCLK(MHz) = [D+1] , OSC= 14.318 (MHz) This bit is used to divide the internal generated oscillation frequency. A logical 0 indicates to do it divided by two. A logical 1 indicates to do it divided by four . Normally, we set to logical 1 when MCLK outputs frequency lower 50MHz.
Bit 7
Extended Indexed Register SREG CA : MCLK Denominator and Post Scalar Value Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 4D.
D0 MCLK post scalar D1-7 MCLK denominator bit 0 to 6
P.54
Bit 0-7
This register,in conjunction with MCLK Numerator Value Register, is used to determine the frequency of memory clock.
Extended Indexed Register SREG CB: Clock Generator Test Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4 D5 D6 D7
Bit 0-1
MCLK/VCLK signal output from OFF pin enable VCLK generated selection Select MCLK as VCLK source Enable pixel clock divide by two for TV display MCLK frequency synthesizer off enable VCLK frequency synthesizer off enable Oscillator off enable
These bits are used to select MCLK/VCLK signal output from OFF pin. Bit 1 Bit 0 Output signal from OFF pin 0 0 Other signal 0 1 Internal MCLK signal 1 X Internal VCLK signal These bits are used to select VCLK clock source . Bit 3 Bit 2 VCLK generated selection 0 0 From VCLK frequency synthesizer 0 1 MCLK synthesizer output dividing by 2 as the VCLK 1 0 VCLK synthesizer output dividing by 2 as the VCLK 1 1 From MCLK frequency synthesizer A logical 1 forces TP6508 video clock frequency divide by two to generated the composite sync. signal for TV display . A logical 1 forces TP6508 to power off MCLK frequency synthesizer. A logical 1 forces TP6508 to power off VCLK frequency synthesizer. A logical 1 forces TP6508 to power off Oscillator.
Bit 2-3
Bit 4 Bit 5 Bit 6 Bit 7
Extended Indexed Register SREG CC: MISC. Control Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4-5 D6 D7
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4-5
DAC monitor senser off enable DAC off enable Synchronous reset timing generator VGA palette off enable Host bus memory access data bus select Emulation 16-bit access disable for 16 color display modes Bypass internal pallete enable
A logical 1 forces TP6508 to power off Monitor Sense logical block. A logical 1 forces TP6508 to power off DAC block and disable CRT display refresh. When logical 1 we can used this bit to reset TP6508 timing generator and synchronize the internal state machine. A logical 1 forces TP6508 VGA palette power off. These bits are used to set the host bus memory access data width.
P.55
Bit 6 Bit 7
Bit 5 Bit 4 Data width 0 0 8-bit 0 1 16-bit 1 0 32-bit 1 1 32-bit or 16-bit This bit is used to set the host-to-display memory bus width on 16 color modes. A logical 1 enables TP6508 to expand to 16-bit data bus access. A logical 0 forces TP6508 to access in 8-bit data bus. A logical 1 forces the pixel data bypass the internal palette and transfer through a special logical block to do as internal palette. In high speed video clock mode , the lookup internal palette operation is critical .
Extended Indexed Register SREG CD: Display Memory Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-1 D2 D3 D4 D5 D6 D7
Bit 0-1
Display memory configuration Asymmetical/symmetical address select for DRAM-A & B Dual-Write/Dual-Cas select for DRAM-A & B Asymmetical/symmetical address select for DRAM-C Dual-Write/Dual-Cas select for DRAM-C Enable 2M-byte display memory size Reserved
These bit are used to configure the DRAMs interface. Bit 1 Bit 0 Display Memory Bus Width & Configuration 0 0 32-bit, Enable DRAM-A & DRAM-B interface 0 1 16-bit, Enable DRAM-A only 1 0 32-bit, Enable DRAM-A & DRAM-C interface * 1 1 Reserved (*: DRAM-C isn't used as an external frame buffer with this setting, but does as display memory.) A logical 0 indicates TP6508 to support symmetical DRAM memory addressing for DRAM-A & B. A logical 1 indicates TP6508 to support asymmetical DRAM memory addressing. A logical 0 indicates TP6508 to support dual-CAS DRAM memory addressing for DRAM-A & B. A logical 1 indicates TP6508 to support dual-WRITE DRAM memory addressing. A logical 0 indicates TP6508 to support symmetical DRAM memory addressing for DRAM-C. A logical 1 indicates TP6508 to support asymmetical DRAM memory addressing. A logical 0 indicates TP6508 to support dual-CAS DRAM memory addressing for DRAM-C. A logical 1 indicates TP6508 to support dual-WRITE DRAM memory addressing. A logical 1 enables TP6508 is operated on 2M-byte size memory configuration . Under the condition , TP6508 will adjust some of the counter length of the CRTC and size again the domain of display memory address. Reserved.
Bit 2 Bit 3 Bit 4 Bit 5 Bit 6
Bit 7
Extended Indexed Register SREG CE: Configuration Register 1
This is a read only register. Port address is Hex 3C5. Default value after hardware reset is Hex FF. (Chip internal pull high during power on reset)
D0 D1 D2
Enable BIOS ROMCS* signal output from OFF pin Enable 64k VGA BIOS decoding Relocation VGA BIOS address
P.56
D3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2
Enable IO 16 bit access VGA subsystem enable port address set to Hex46E8(default 3C3) Select VGA subsystem power-on in enable state Enable ISA bus width 8 bit Select SA address decoder (These bits are latched from MAD0 to MAD7 at power on reset.)
When bus interface was selected VESA/CPU direct local bus connection , then this can set to logical 1 to enable BIOS ROMCS* signal output from OFF/EPROM* pin(pin 178). We can set this bit to logical 0 to enable TP6508 BIOS decoding to expansion to 64 kb address domain. When previous bit was set to logical 1, then this bit can be setting to relocate VGA BIOS decoding address. Bit 2 Decoding address 0 Hex E0000 to EFFFF 1 Hex C0000 to CFFFF A logical 0 enables TP6508 IO 16 bit access. This bit selects the address of the video subsystem enable bit location. A logical 0 indicates the address of the video subsystem bit is Hex 46E8 , a logical 1 indicates that it is located on the address Hex 3C3. A logical 0 indicates TP6508 power-on in the enable state that allows memory and IO accessing . A logical 1 indicates TP6508 in the disable state at power-on. A logical 0 forces TP6508 connects to 8 bit width host bus . A logical 1 forces TP6508 connects to 16 bit width host bus. A logical 1 indicates TP6508 use ALE signal to latch LA address signal . A logical 0 indicates TP6508 directs to decode SA address by bus command signals (MEMW*,MEMR*,IOW*,IOR*) .
Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
Extended Indexed Register SREG CF: Configuration Register 2
This is a read only register. Port address is Hex 3C5. Default value after hardware reset is Hex FF. (Chip internal pull high during power on reset)
D0-2 TP6508 into Test mode selection bit (Latched from MD 4 to 5) D3 Reserved D4-7 Display type selection bits (These bits are latched from MAD8 to MAD15 at power on reset.)
Bit 0-2 These bit is used to enable TP6508 into test mode for the internal analog device blocks, including of the dual frequency synthesizer and RAMDAC . We can directly access the internal analog device blocks by TP6508's I/O pins. Bit 2 Bit 1 Bit 0 Test device 1 1 0 MCLK analog device function test mode 1 0 1 VCLK analog device function test mode 0 1 1 DAC analog device function test mode Reserved. These bits are used to read back for VGA BIOS setting display type . Bit-7 Bit-6 Bit-5 Bit-4 Display Type 0 0 0 0 NTSC TV 0 0 0 1 LCD/NTSC TV 0 0 1 0 800x600 color TFT 0 0 1 1 800x600 color DSTN 0 1 0 0 CRT-like TFT 0 1 0 1 Dual-scan STN LCD 0 1 1 0 800x600 color TFT P.57
Bit 3 Bit 4-7
0 1 1 1 1 1 1 1 1
1 0 0 0 0 1 1 1 1
1 0 0 1 1 0 0 1 1
1 0 1 0 1 0 1 0 1
800x600 color DSTN CRT/PLASMA CRT/EL CRT/Line-clock TFT CRT/CRT-like TFT CRT/Single-scan STN LCD CRT/Dual-scan STN LCD CRT/Mono LCD CRT
Extended Indexed Register SREG D0: Configuration Register 3
This is a read only register. Port address is Hex 3C5. Default value after hardware reset is Hex FF.
D0-2 D3 D4 D5 D6 D7
Bit 0-2
Host bus selection bit 0 to 2 (Latched from AA0 to AA2) Disable A24 pin input data latch (Latched from AA3) Disable internal dual frequency synthesizer (Latched from AA4) Reserved (Latched from AA5) Reserved=1 (Latched from AA6) Disable PCI bus command asserted on configuration registers accessing (Latched (Latched from AA7)
In addition to an ISA bus connection, TP6508 can be connected directly to VESA local bus , PCI local bus or 486DX/DX2 local bus to provide additional graphics performance. Bit 2 Bit 1 Bit 0 Host bus selection 0 0 0 Reserved 0 0 1 Reserved 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Reserved 1 0 1 ISA bus 1 1 0 32-bit PCI Local Bus 1 1 1 Reserved A logical 1 enables TP6508 to decode A24 pin input for linear address . This configuration bit must set to 1 for VESA/CPU local bus . A logical 0 forces TP6508's internal dual frequency synthesizer not in operation. That make TP6508 to select the multiple pin OFF and XTALI as VCLK and MCLK pin . The source of video clock and memory clock are come from external component by VCLK and MCLK pin . Reserved. Reserved. We can set this bit to logical 0 to force TP6508 not to assert a VGA access cycle on PCI local bus interface under the configuration read or write command being happend..
Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
Extended Indexed Register SREG D1: GEC. Test Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Bit 0-7 Reserved.
P.58
Extended Indexed Register SREG D2: Power Management Control Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2 Bit 3
Reserved Select OFF pin as input pin Select OFF pin control as active high control signal Select standby timer as suspend timer Force into standby mode Force into suspend mode Force into off mode Select Cover-Close mode (CRT display only this bit must =1)
Reserved. A logical 1 select OFF pin as input pin, and a logical 0 select it as output pin. A logical 0 select OFF pin signal polarity as active low, and a logical 1 select OFF pin signal polarity as active high. A logical 1 select standby timer as suspend timer, then we can program this timer to change state from active mode to suspend mode and not to standby mode. A logical 0 we can program this timer to change state from active mode to standby mode. User can to change state from active mode to standby mode by software programming this bit to logical 1. User can to change state to suspend mode by software programming this bit to logical 1. User can to change state to off mode by software programming this bit to logical 1. A logical 1 select into Cover-close mode. Cover-close mode is the special power mode using for laptop PC or notebook pc system on closing the machine-cover . Specially, this mode replace off mode when the user programmed this bit to logical 1 . In cover-close mode, system will turn off panel backlight, and down saving internal partial panel block device power. Then the CRT display is normal.
Bit 4 Bit 5 Bit 6 Bit 7
Extended Indexed Register SREG D3: Backlight and Standby Timer Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-3 Timer for backlight control bit 0 to 3 (Unit : 1 minute error -1/16 minute) D4-7 Timer for standby/suspend control bit 0 to 3 (Unit : 2 minute error -1/8 minute) (User can use the value of 00 to disable the timer for power management .)
Bit 0-3 These bits are used to program the time that panel's backlight turn off after active mode into standby mode . The timer clock base is 14.318MHz for internal C.G. or external OSC. pin clock input divided by 4 . These bits are used to program the time that active mode go into standby/suspend mode after the system was in the rest state.
Bit 4-7
Extended Indexed Register SREG D4 : Activity Monitoring Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2-3 D4
Enable VGA access to reset backlight timer Enable Keyboard activity to reset backlight timer Reserved Enable VGA access to reset standby/off timer
P.59
D5 Enable Keyboard activity to reset standby/off timer D6-7 Reserved
Bit Bit Bit Bit Bit Bit 0 1 2-3 4 5 6-7 A logical 1 enables TP6508 to reset backlight timer for flat panel by VGA access. A logical 1 enables TP6508 to reset backlight timer for flat panel by keyboard activity. Reserved A logical 1 enables TP6508 to reset standby timer for flat panel by VGA access. A logical 1 enables TP6508 to reset standby timer for flat panel by keyboard activity. Reserved
Extended Indexed Register SREG D5 : OFF Timer and Slow Refresh Register
This is a read only register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-3 D4 D5-6 D7
Bit 0-3 Bit 4 Bit 5-6
Timer for off control bit 0 to 3 (Unit : 4 minute error -1/4 minute) Enable slow refresh in off mode Slow refresh rate selection bit 0 to 1 Select external 32kHz clock as power management clock base
These bits are used to program the time that active mode go into off mode after the system was in the rest state. A logical 1 enables TP6508 to slow down the refresh rate that specifies by next two bits in the off mode. When TP6508 goes into off mode , it provide programmable refresh rate for power saving . Bit 6 Bit 5 Refresh rate (KHz) 0 0 No refresh 0 1 32 1 0 16 1 1 8 User can use this bit to select the power management clock source. A logical 0 TP6508 selects the internal refresh clock base being divided the frequency of 14.318MHz clock source . And a logical 1 TP6508 switches the clock source to external 32KHz clock input.
Bit 7
Extended Indexed Register SREG D6 : Override and Status control Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00. D0 D1 D2 D3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2
FPBACK output override FPBACK polarity FPVCC/FPSIG/FPVEE output override FPVCC status FPSIG output status FPVEE output status Panel control state machine test mode enable FPVEE Pin(pin 61) output control
A logical 1 indicates TP6508 would override FPBACK standby mode. If previous bit =1, then programming this bit would set the output state of FPBACK. If previous bit =0, then bit is used to invert the FPBACK output polarity. A logical 1 indicates TP6508 would override FPVCC standby mode . P.60
Bit 3 Bit 4
Bit 5 Bit 6 Bit 7
If previous bit =1 , then programming this bit would set the output state of FPVCC. If bit2 =1 , then programming this bit would set the output state of panel control signal (FPVDCLK,MOD,LFS,LLCLK,DE*) and panel data bus. A logical 0 forces TP6508 set these output to logical 0 . A logical 1 indicates these signals output normal . If bit2 =1 , then programming this bit would set the output state of FPVEE. The bit is used to enable the panel control state machine into test mode (short the power sequency cycle time) . It is to be enable for internal test only. A logical 0 enables TP6508 output FPVEE signal from Pin 61. A logical 1 enables TP6508 output FPBACK signal from Pin 61.
Extended Indexed Register SREG D7 : Memory mapping I/O Offset Low Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Graphics engine memory mapping I/O command offset bit 0 to 7
Bit 0-7 When memory map I/O was enabled (SREG bit-3=1), these bits would use to do as the segment address of I/O command for replacing the address A16 to A23. We can set these bits to relocate the I/ O port address of Graphics Engine registers. By memory map I/O addressing, these registers are accessed as memory command and located at memory address binary ZZZZ,ZZZZ,ZZZZ,xxxx,xxYY,YYYY,YY00. The address value - 'Z..' is determined by this register and SREG D8. The low address value - 'Y..' is determined by SREG F0. The address value - 'x..' is determined by the Graphics Engine control register indexed value. Then TP6508 can access these registers with 16-bit data width by decoding at them, being conjunction with 'Y..' and 'x..' , directly.
Extended Indexed Register SREG D8 : Memory mapping I/O Offset High Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-3 Graphics engine memory mapping I/O command offset bit 8 to 11 D4-7 Reserved
Bit 0-7 When memory map I/O was enabled, these bits would use to do as the segment address of I/O command for replacing the address A24 to A27.
Extended Indexed Register SREG D9 : PC Video Control Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3-7
Bit 0 Bit 1
Enable PC Video interface Select PC Video width Enable PC Video color key Reserved
A logical 1 enables PC video interface on DRAM-C pins that includes of RASC* ,CASCH* ,CASCL* ,WEC* , MCD[15:0]. A logical 0 disables it. When previous bit is set to logical 1, this bit is used to select the PC video interface width. A logical 0 forces TP6508 inplements a 18-bit width PC video interface. A logical 1 enables TP6508 inplements a 24-bit width PC video interface and sets OEC*,AA9,FPBACK,ACTI as video input. When this bit is set to logical 1, a 24-bit panel interface is also avilable by CA[7:0] being becomed P[23:16]. Specially, this bit shouldn't be set to 1 if the SREG D0 bit-6 is set to 1. P.61
Bit 2
Bit 3-7
If the previous bit-0 is set to logical 1 , then this bit is used to select the color key type for PC video Overlay . A logical 1 forces TP6508 use external color key signals and enables PC video Overlay on color key. A logical uses the following color compare registers to generate the color key . Reserved.
Extended Indexed Register SREG DA : Color Key Compare Register 0
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare data bit 0 to 7
Bit 0-7 These bits are compared to bit 0 to 7 of background video stream. They are in conjunction with color compare bit 8 to 15 and color compare bit 16 to 23 to compare with color key data. When all the enabled bits that are set by mask regs. SREG DB/DC/DD matches the relation color key data bits and the key is enabled, external video sent to the screen.
Extended Indexed Register SREG DB : Color Key Compare Register 1
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare data bit 8 to 15
Bit 0-7 These bits are compared to bit 8 to 15 of background video stream. They are in conjunction with color compare bit 0 to 7 and color compare bit 16 to 23 to compare with color key data. When all the enabled bits that are set by mask regs. SREG DB/DC/DD matches the relation color key data bits and the key is enabled, external video sent to the screen.
Extended Indexed Register SREG DC : Color Key Compare Register 2
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare data bit 16 to 23
Bit 0-7 These bits are compared to bit 16 to 23 of background video stream. They are in conjunction with color compare bit 0 to 7 and color compare bit 8 to 15 to compare with color key data . When all the enabled bits that are set by mask regs. SREG DB/DC/DD matches the relation color key data bits and the key is enabled, external video sent to the screen.
Extended Indexed Register SREG DD : Color Key Mask Register 0
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare mask bit 0 to 7
Bit 0-7 These bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. This register control bits 0 to 7. The mask data bits format are as follow: 0: Data does particpate in compare operation 1: Data mask in compare operation
P.62
Extended Indexed Register SREG DE : Color Key Mask Register 1
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare mask bit 8 to 15
Bit 0-7 These bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. This register control bits 8 to 15.
Extended Indexed Register SREG DF : Color Key Mask Register 2
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Color compare mask bit 16 to 23
Bit 0-7 These bits are used to select which bits of the background video data stream are used in the comparsion with the color compare data bit 0 to 23. This register control bits 16 to 23.
Extended Indexed Register SREG F0 : Graphics Engine Port Address Low Register
This is a read only register. Port address is Hex 3C5. Default value after hardware reset is Hex F1.
D0-7 Graphics engine port address bit 2 to 9
Bit 0-7 TP6508 Graphics Engine control registers are accessed at Port binary address xxxx,xxYY,YYYY,YY00. These bits are used to determine the low address value - 'Y..' and they are set default hex. F1. The high address value - 'x..' is determined by Graphics Engine control registers indexed value. For example, as default value hex. F1, BITBLT Source X Offset Reg. port address at hex. 07C4.
Extended Indexed Register SREG F1 : Linear Addressing Register
This is a read/write register. Port address is Hex 3C5. Default value after hardware reset is Hex 00.
D0-7 Base address bit 0 to 7
Bit 0-7 When SREG C0 bit-2 was set to logical 1 , then these bits would use to do as LA20 to LA27. IBM compatible display address uses low base 1M address bit 0 to 19 and locates at Hex A0000 to AFFFF or Hex B0000 to BFFFF. We can set these bits to relocate display address at upper high 255M memory address.
P.63
Extended CRTC Register Description
The following registers are TP6508 extended CRTC registers. These registers are accessed by first writing the index of the desired register to the Sequencer Index register, i.e. address Hex 3D4 and then accessing the register using the address Hex 3D5. These registers are protected by password/ Identification register (Extended Sequencer Indexed Register Hex 05) .
Extended Indexed Register CREG 20 : Extended memory address offset Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended memory address offset bit 0 to 7
Bit 0-7 In TP6508 interlace display design , you can use this register to program the memory address offset value as the memory length of one scan line to next scan line during odd or even filed for interlace display mode . The bit 8 are in the bit 4 of Extended register CREG 21.
Extended Indexed Register CREG 21 : Memory address offset High Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 D1-3 D4-5 D6-7
Bit Bit Bit Bit 0 1-3 4-5 6-7
Extended memory address offset bit 8 Reserved IBM Memory address offset bit 8,9 Reserved
Extended memory address offset bit 8. Reserved. Memory address offset bit 8 to 9. Reserved.
Extended Indexed Register CREG 22 : Start Address High Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 Start address bit 16 to 19 D4-7 Cursor address bit 16 to 19
Bit 0-3 The most significant bit 16 and bit 19 of the start address register. Bit 4-7 The most significant bit 16 and bit 19 of the cursor address register.
Extended Indexed Register CREG 23 : Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Bit 0-7 Reserved.
P.64
Extended Indexed Register CREG 24 : CRT Vertical High Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5-7
Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5-7
Vertical total bit 10 Vertical display enable end bit 10 Vertical blank star bit 10 Vertical retrace start bit 10 Line compare bit 10 Reserved
Bit 10 of the vertical total register. Bit 10 of the vertical display enable register. Bit 10 of the vertical blank start register. Bit 10 of the vertical retrace start register. Bit 10 of the line compare register. Reserved.
Extended Indexed Register CREG 25 : Half Horizontal Retrace Start Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Half horizontal retrace start bit 0 to 7
Bit 0-7 In interlace display mode , TP6508 need a count point that point at half of a scan-line to generate the interlace display timing sequence . And these bits are nice to program doing it , a real interlace display .
Extended Indexed Register CREG 26 : TV Leading Horizontal Retrace Start Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 TV leading horizontal retrace start bit 0 to 7
Bit 0-7 By TV display, it was designed to base on the interlace scan technique, TP6508 need two retrace signal(like VGA retrace signal) on even field and odd field. TV composite sync. signal waveform include two equalizing pulse interval, front and back the vertical sync. interval, those have three pulse individually. We need to define the intervals position in the TV composite sync. waveform. So we can use these bits to program the front equalizing pulse(front of horizontal sync. pulse interval ) start position. on even field and make it be able using in TV display mode.
Extended Indexed Register CREG 27 : TV Horizontal Retrace End for Equalizing Pulse Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 TV horizontal retrace end bit 0 to 3 D4-7 Reserved
Bit 0-3 These bits is used to program the back equalizing pulse(back of horizontal sync. pulse interval ) start position. on even field and make it be able using in TV display mode. P.65
Bit 4-7
Reserved .
Extended Indexed Register CREG 28 : TV Leading Half Horizontal Retrace Start Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 TV leading half horizontal retrace start bit 0 to 3 D4-7 Reserved
Bit 0-3 By TV display, it was designed to base on the interlace scan technique, TP6508 need two retrace signal(like VGA retrace signal) on even field and odd field. TV composite sync. signal waveform include two equalizing pulse interval, front and back the vertical sync. interval, those have three pulse individually. We need to define the intervals position in the TV composite sync. waveform. So we can use these bits to program the front equalizing pulse(front of horizontal sync. pulse interval ) start position. on even field and make it be able using in TV display mode. Reserved .
Bit 4-7
Extended Indexed Register CREG 29 : TV Half Horizontal Retrace End for Equalizing Pulse Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 TV leading half horizontal retrace end bit 0 to 3 D4-7 Reserved
Bit 0-3 Bit 4-7 These bits is used to program the back equalizing pulse(back of horizontal sync. pulse interval ) start position. on odd field and make it be able using in TV display mode. Reserved .
P.66
Panel Control Register Description
The following registers are TP6508 Panel Control registers. These registers are accessed by first writing the index of the desired register to the Sequencer Index register, i.e. address Hex 3D4 and then accessing the register using the address Hex 3D5. These registers are protected by password/ Identification register (Extended Index Register Hex 05) .
Extended Indexed Register CREG A0 : Panel Miscellaneous Control Register 1
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-2 D3 D4 D5 D6 D7
Bit 0-2 Bit 2 0 0 0 0 1 1 1 1 Bit Bit Bit Bit 3 4 5 6
Flat panel type 0 to 2 Invert LP/PHSYNC control Invert FLM/PVSYNC control invert FPVDCLK/PSCLK Free run LLCLK Invert DEN control
These three bits select the type of Flat panel connected. Bit 1 Bit 0 Panel type 0 0 Dual-Scan/Dual-data Monochrome LCD panels 0 1 Gray scale PLASMA panels 1 0 Single-Scan STN color LCD panels 1 1 TFT color LCD panels 0 0 Reserved 0 1 Gray scale EL panels 1 0 Dual-Scan STN color LCD panels 1 1 Reserved A logical 1 would invert the LLCLK signal (normally active high). A logical 1 would invert the LFS signal (normally active high). A logical 1 would invert the FPVDCLK signal (normally active high). The last line of every frame may display longer and brighter than other lines. When this bit is a logical 1 , it forces TP6508 to generate a free-running LLCLK and eliminates the brighter line during CRT blanking cycle. A logical 1 would invert the DEN signal (normally active high) for PLASMA or TFT panel display mode .
Bit 7
Extended Indexed Register CREG A1 : Panel Miscellaneous Control Register 2
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5
Select 8 bits color STN interface Select enhance color STN timing Select CRT-like LP and FLM for TFT LCD panel Disable CRT display Enable Flat panel interface Select 8 bit PLASMA panel interface
P.67
D6 D7
Bit Bit Bit Bit Bit Bit 0 1 2 3 4 5
Select gray conversion type for mono flat panel display Enable TV display
A logical 1 TP6508 selects 8 bits color STN interface A logical 1 TP6508 switches the panel display timing to enhance color STN timing. A logical 1 TP6508 selects CRT-like LP(Hsync) and FLM(Vsync) for TFT LCD panel. A logical 1 disables the CRT display , and a logical 0 enables it. A logical 1 enables the flat panel display, and a logical 0 disables the flat panel display. A logical 1 TP6508 selects 8 bits PLASMA interface . And a logical 0 TP6508 selects 4 bits PLASMA interface. This bit is use to set the gray conversion type for mono flat panel display . A logical 1 enable it , a logical 0 disable it. A logical 1 enables the TV display and we can output composite SYNC signal to HSYNC pin.
Bit 6 Bit 7
Extended Indexed Register CREG A2 : Panel Miscellaneous Control Register 3
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00. D0 D1 D2-3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2-3
Reverse panel video output for text mode Reverse panel video output for graphic mode Blinking rate selection bit 0 to 1 Select maximum contrast display for text mode Select attribute emulation display for text mode Select RGBI emulation display for 16 color graphic mode Enable full cursor display for text mode
A logical 1 reverses the pixel data that sends to the panel for text mode . A logical 1 reverses the pixel data that sends to the panel for graphic mode . LCD panel has low response time character, TP6508 provides flexible choice for blinking rate. Bit 3 Bit 2 Blinking Rate 0 0 1/16 0 1 1/32 1 0 1/64 1 1 1/128 In panel text mode, when foreground RGB and background RGB mapping to the close gray level. It will produce ambiguous phenomenon. When this bit is a logical 1, TP6508 will compare foreground and background mapping gray level. If foreground gray level is larger than background gray level, TP6508 forces foreground to the maximum gray level , background to the minimum gray level . It will eliminate ambiguous situation. If the bit 6 of previous register set to logical 1 , then this bit is not valid . When this bit is a logical 1, TP6508 provides 16 gray level without passing through gray palette for text mode . In this mode, Red, Green, Blue, and Intensity , four bits can make 16 gray level without losing color, mono mapping relation . When this bit is a logical 1, TP6508 provides 16 gray level without passing through gray palette for 16 color graphic mode. On LCD panel, a narrow cursor may difficult to observe. A logical 1 forces a full display cursor for easy find out and ignores the cursor sharp setting.
Bit 4
Bit 5
Bit 6 Bit 7
P.68
Extended Indexed Register CREG A3 : Panel Miscellaneous Control Register 4
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5 D6 D7
Bit 0 Bit 1 Bit 2
Enable vertical expansion for text mode Enable vertical expansion for graphic mode Force 8 dots character clock Enable shadow frame buffer with internal Line buffer for Mono Dual-scan STN LCD Enable shadow frame buffer with internal Line buffer for Color Dual-scan STN LCD Enable external frame buffer for Color Dual-scan STN LCD Enable extra LLCLK 244 Enable extra LLCLK 242
A logical 1 forces TP6508 to fit the panel vertical resolution for text mode. A logical 1 forces TP6508 to fit the panel vertical resolution for graphic mode. In panel mode , LCD and PLASMA manufactures produce 640x480 pixel panel . Some IBM standard modes define 9 dots per character , all characters cannot display 80 columns (720 dots) at the same time . When this bit is a logical 1, TP6508 force character width to be 8 dots. In monochrome dual-scan STN LCD display,logical 1 enables shadow frame accelerate operation. At this time, TP6508 can gain better display quality and up to 64 gray level. Other flat panel display modes this bit is invaild . In color dual-scan STN LCD display,logical 1 enables shadow frame accelerate operation. At this time, TP6508 can gain better display quality and up to 64k color level . Other flat panel display modes this bit is invaild . In color dual-scan STN LCD display, logical 1 enables external frame accelerate operation to gain better display quality. At this time an extra DRAM(s) is necessary . A logical 0 disables the external frame buffer and TP6508 uses the Pseudo Frame Buffer technique to implement the display mode . Other display mode this bit is invaild . A logical 1 enables one extra LLCLK for LCD monochrome panels that require 244 line clocks for the upper panel. A logical 1 enables one extra LLCLK for LCD monochrome panels that require 242 line clocks for the upper panel.
Bit 3
Bit 4
Bit 5
Bit 6 Bit 7
Extended Indexed Register CREG A4 : LCD AC Modulation Period Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 LCD AC modulation bit 0 to 7
Bit 0-7 AC modulation LCD panel cannot be driven in the DC level. Some LCD panel modules do not provide AC modulation signal, TP6508 offers this function to prevent LCD damage. These bits define the number of LP(Hsync) between adjacent phase changes on MOD output. As these bits are programmed to hex 00, then the MOD signal phase changes every frame.
Extended Indexed Register CREG A5 : Panel Miscellaneous Control Register 5
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00. D0 Panel resolution selection
P.69
D1 D2 D3 D4 D5-7
Bit 0
Select 600-line Extended CRT vertical group registers Enable horizontal expansion for text mode Enable horizontal expansion for graphic mode Enable TV equalizing pulse Reserved
This bit is used to select the flat panel resolution .(for vertical expansion and horizontal centering) 0: 640x flat panel size 1: 800x flat panel size This bit is used to select the extended vertical timing set register group when the bit-1 of CREG AC(Enable extended vertical timing) was set to logical 1 and the bit-6,7 of MISCREG were set to 1,1. The more description is in CREG AC bit-1 description. 0: Use the 480-line vertical timing CRT regs. CREG B6-BC 1: Use the 600-line vertical timing CRT regs. CREG C7-CD A logical 1 forces TP6508 to fit the panel horizontal resolution for text mode. A logical 1 forces TP6508 to fit the panel horizontal resolution for graphic mode. This bit is used to select the TV composit signal generated type. 0: No equalizing pulse, it only composits horizontal and vertical sync. 1: Insert equalizing pulse Reserved.
Bit 1
Bit 2 Bit 3 Bit 4
Bit 5-7
Extended Indexed Register CREG A6 : Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Extended Indexed Register CREG A7:Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Extended Indexed Register CREG A8 : X Offset Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-4 LCD panel gray modulation X offset bit 0 to 4 D5-6 TFT LCD panel amplitude modulation bit 0 to 1 D7 Reserved
Bit 0-4 Bit 5-6 TP6508 has a special function to eliminate stippling wave . You can program X-directional offset values for best looking. User can use the amplitude modulation to smooth and get to colorfully by these two bits. Bit 6 Bit 5 Description 0 0 Disable amplitude modulation 0 1 Select two bits and Ground signal modulation (data bit 1 to 0) 1 0 Select three bits modulation (data bit 2 to 0) 1 1 Select three bits modulation (data bit 3 to 1) Reserved P.70
Bit 7
Extended Indexed Register CREG A9 : Y Offset Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-4 LCD panel gray modulation Y offset bit 0 to 4 D5-6 Flat panel dithering type bit 0 to 1 D7 Dither algorithm selection
Bit 0-4 Bit 5-6 TP6508 has a special function to eliminate stippling wave . You can program Y-directional offset values for best looking. User can select the dithering type to smooth and get to colorfully by these two bits. Bit 6 Bit 5 Description 0 0 Disable dithering function 0 1 Select two bits dithering (data bit 1 to 0) 1 0 Select two bits dithering (data bit 2 to 1) 1 1 Select two bits dithering (data bit 3 to 2) This bit is used to select the dither algorithm method. A logical 0 select the color modulation bit to be the next bit of the two selected dithering bits in bit 5-6 of this register. A logical 1 select the color modulation bit to be the LSB of the color data.
Bit 7
Extended Indexed Register CREG AA : Frame Buffer Start Address High register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 D4 D5 D6 D7
Bit 0-3
Frame buffer start address bit 0 to 3 Reserved M Pin selection LP Pin selection Reserved
With integrated frame accelerator technology . TP6508 can use the video memory space as internal frame buffer to replace the external frame buffer . These bits is programming to set the internal frame buffer starting address of video memory. They replace and do as memory address MA14 to MA17. Reserved. This bit is used to select the M Pin(pin 69) output function. Bit 5 Output function 0 M signal output 1 DE* signal output This bit is used to select the LP Pin(pin 68) output function. Bit 6 Output function 0 LP signal output 1 DE* signal output Reserved.
Bit 4 Bit 5
Bit 6
Bit 7
Extended Indexed Register CREG AB : Line Buffer Terminal Count Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-5 Line buffer terminal count bit 0 to 5 (Unit : 32 pixels) D6-7 Reserved
P.71
Bit 0-5
Bit 6-7
TP6508 has a internal line buffer to store pixel-data of a line for dual flat panel device. Specially, the line buffer must work on the condition that TP6508 has turned on panel frame buffer and it do as a temp store of frame buffer. These bits can be programmed to set the line buffer length which base on flat panel horizontal resolution or do for simulation test only. Reserved.
Extended Indexed Register CREG AC : Extended CRT Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 D1 D2 D3 D4 D5 D6-7
Bit 0
Enable extended horizontal timing set Enable extended vertical timing set IBM CRT control registers lock Half panel timing source selection Text mode vertical expansion selection Enable 24-bit TFT panel interface Reserved
A logical 1 forces TP6508 using the extended CRT horizontal timing set registers to match or fit the flat panel resolution for LCD or LCD-CRT display mode. A logical 0 set TP6508 working on using the IBM CRT horizontal timing set registers. A logical 0 set TP6508 working on using the IBM CRT vertical timing set registers . A logical 1 forces TP6508 using the extended CRT vertical timing set registers to match or fit the flat panel resolution for LCD or LCD-CRT display mode. Then, we can use the MISCREG bit 6,7 to select the extended vertical timing set register group. The more description is in CREG A5 bit-3 description. MISCREG Bit-7, Bit-6 Selected Vertical CRT register group 0 0 Reserved 0 1 Use the 400-line vertical timing CRT regs. CREG C7-CD 1 0 Use the 350-line vertical timing CRT regs. CREG C7-CD 1 1 Decided by CREG A5 bit-3 A logical 1 enables CRTC lock to protect the parameter of IBM CRT control register. A logical 0 inducates TP6508 to generate the half panel timing by setting Ext. Reg. hex A5 for internal panel controller use . A logical 1 forces TP6508 use the half of VDE signal as it by programming the CRT Reg. hex 12. A logical 0 selects to insert a line by counting every 3 or 5 lines for x350 or x400 resolution text mode to fit the vertical resolution of flat panel . A logical 1 selects to insert 5 or 3 line into every character for x350 or x400 resolution text mode to fit the vertical resolution of flat panel . A logical 1 enables TP6508 to implement 24-bit panel interface for 18-bit or 24-bit TFT panel. A logical 0 forces TP6508 to implement 16-bit panel interface for 9/12/15/16-bit panel. Reserved
Bit 1
Bit 2 Bit 3
Bit 4
Bit 5 Bit 6-7
Extended Indexed Register CREG AD : Extended CRT Horizontal Total Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT horizontal total bit 0 to 7 (-5 )
Extended Indexed Register CREG AE : Extended CRT Horizontal Display Enable End Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00. P.72
D0-7 Extended CRT horizontal display enable end bit 0 to 7 (-1)
Extended Indexed Register CREG AF : Extended CRT Horizontal Blanking Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT horizontal blanking start bit 0 to 7 (-1)
Extended Indexed Register CREG B0 : Extended CRT Horizontal Blanking End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-5 Extended CRT horizontal blanking end bit 0 to 5 D6-7 Reserved
Extended Indexed Register CREG B1 : Extended CRT Horizontal Retrace Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT horizontal retrace start bit 0 to 7
Extended Indexed Register CREG B2 : Extended CRT Horizontal Retrace End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-4 Extended CRT horizontal retrace end bit 0 to 4 D5-7 Reserved
Extended Indexed Register CREG B3 : Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Extended Indexed Register CREG B4 : Extended CRT Horizontal Retrace Start for TFT LCD panel
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT horizontal retrace start bit 0 to 7 for TFT LCD panel
Extended Indexed Register CREG B5 : Extended CRT Horizontal Retrace End for TFT LCD panel
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-4 Extended CRT horizontal retrace end bit 0 to 4 for TFT LCD panel D5-7 Extended CRT horizontal retrace skew bit 0 to 2 for TFT LCD panel
P.73
Extended Indexed Register CREG B6 : 480-Line Extended CRT Vertical Total Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical total bit 0 to 7 (-2)
Extended Indexed Register CREG B7 : 480-Line Extended CRT Vertical Display Enable End Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical display enable end bit 0 to 7 (-1)
Extended Indexed Register CREG B8 : 480-Line Extended CRT Vertical Blank Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank start bit 0 to 7 (-1)
Extended Indexed Register CREG B9 : 480-Line Extended CRT Vertical Blank End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank end bit 0 to 7
Extended Indexed Register CREG BA : 480-Line Extended CRT Vertical Retrace Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical retrace start bit 0 to 7
Extended Indexed Register CREG BB : 480-Line Extended CRT Vertical Retrace End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 Extended CRT vertical retrace end bit 0 to 3 D4-7 Reserved
Extended Indexed Register CREG BC : 480-Line Extended CRT Vertical Overflow
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4-5 D6-7
Extended CRT vertical total bit 8 to 9 Extended vertical display enable end bit 8 to 9 for vertical expansion mode Extended CRT vertical blank start bit 8 to 9 Extended CRT vertical retrace start bit 8 to 9
P.74
Extended Indexed Register CREG C0 : Flat Panel 350 Scan line Mode Display Centering Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 LCD panel 350 scan line mode screen shift bit 0 to 7
Bit 0-7 These bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 350 scan line mode. And you can get through the screen display centering.
Extended Indexed Register CREG C1: Flat Panel 400 Scan line Mode Display Centering Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 LCD panel 400 scan line mode screen shift bit 0 to 7
Bit 0-7 These bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 400 scan line mode. And you can get through the screen display centering.
Extended Indexed Register CREG C2: Flat Panel 480 Scan line Mode Display Centering Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 LCD panel 480 scan line mode screen shift bit 0 to 7
Bit 0-7 These bits are used to program the vertical screen shift length from the top or bottom of panel to actual display part on 480 scan line mode. And you can get through the screen display centering.
Extended Indexed Register CREGC3 : Half Panel Size Low Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Half panel size bit 0 to 7
Bit 0-7 These bits use to decide the half panel size (scan lines - 1 ) and make TP6508 generating accurate flat panel interface timing.
Extended Indexed Register CREG C4 : Half Panel Size High Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0 Half panel size bit 8 D1-7 Reserved
Bit 0 Bit 1-7 This bit is the high bit of half panel size register. Reserved. P.75
Extended Indexed Register CREG C5: Flat Panel Text Mode Display Horizontal Centering Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 LCD panel horizontal screen shift bit 0 to 3 for text mode display (in character as unit) D4-7 Reserved
Bit 0-3 Bit 4-7 These bits are used to program the horizontal screen shift length from the left or right of panel to actual display part. And you can get through the screen display centering . Reserved.
Extended Indexed Register CREG C6: Flat Panel Graphics Mode Display Horizontal Centering Control Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 LCD panel horizontal screen shift bit 0 to 3 for graphics mode display ( in character as unit) D4-7 Reserved
Bit 0-3 Bit 4-7 These bits are used to program the horizontal screen shift length from the left or right of panel to actual display part. And you can get through the screen display centering. Reserved.
Extended Indexed Register CREG C7 : 600-Line Extended CRT Vertical Total Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical total bit 0 to 7 (-2)
Extended Indexed Register CREG C8 : 600-Line Extended CRT Vertical Display Enable End Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical display enable end bit 0 to 7 (-1)
Extended Indexed Register CREG C9 : 600-Line Extended CRT Vertical Blank Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank start bit 0 to 7 (-1)
Extended Indexed Register CREG CA : 600-Line Extended CRT Vertical Blank End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank end bit 0 to 7
P.76
Extended Indexed Register CREG CB : 600-Line Extended CRT Vertical Retrace Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical retrace start bit 0 to 7
Extended Indexed Register CREG CC : 600-Line Extended CRT Vertical Retrace End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 Extended CRT vertical retrace end bit 0 to 3 D4-7 Reserved
Extended Indexed Register CREG CD : 600-Line Extended CRT Vertical Overflow
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4-5 D6-7
Extended CRT vertical total bit 8 to 9 Extended vertical display enable end bit 8 to 9 for vertical expansion mode Extended CRT vertical blank start bit 8 to 9 Extended CRT vertical retrace start bit 8 to 9
Extended Indexed Register CREG F0 : 400-Line Extended CRT Vertical Total Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical total bit 0 to 7 (-2)
Extended Indexed Register CREG F1 : Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Extended Indexed Register CREG F2 : 400-Line Extended CRT Vertical Blank Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank start bit 0 to 7 (-1)
Extended Indexed Register CREG F3 : 400-Line Extended CRT Vertical Blank End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank end bit 0 to 7
P.77
Extended Indexed Register CREG F4 : 400-Line Extended CRT Vertical Retrace Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical retrace start bit 0 to 7
Extended Indexed Register CREG F5 : 400-Line Extended CRT Vertical Retrace End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 Extended CRT vertical retrace end bit 0 to 3 D4-7 Reserved
Extended Indexed Register CREG F6 : 400-Line Extended CRT Vertical Overflow
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4-5 D6-7
Extended CRT vertical total bit 8 to 9 Reserved Extended CRT vertical blank start bit 8 to 9 Extended CRT vertical retrace start bit 8 to 9
Extended Indexed Register CREG F7 : 350-Line Extended CRT Vertical Total Register
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT Extended CRT vertical total bit 0 to 7 (-2)
Extended Indexed Register CREG F8 : Reserved
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Reserved
Extended Indexed Register CREG F9 : 350-Line Extended CRT Vertical Blank Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank start bit 0 to 7 (-1)
Extended Indexed Register CREG FA : 350-Line Extended CRT Vertical Blank End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical blank end bit 0 to 7
P.78
Extended Indexed Register CREG FB : 350-Line Extended CRT Vertical Retrace Start
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-7 Extended CRT vertical retrace start bit 0 to 7
Extended Indexed Register CREG FC : 350-Line Extended CRT Vertical Retrace End
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-3 Extended CRT vertical retrace end bit 0 to 3 D4-7 Reserved
Extended Indexed Register CREG FD : 350-Line Extended CRT Vertical Overflow
This is a read/write register. Port address is Hex 3D5. Default value after hardware reset is Hex 00.
D0-1 D2-3 D4-5 D6-7
Extended CRT vertical total bit 8 to 9 Reserved Extended CRT vertical blank start bit 8 to 9 Extended CRT vertical retrace start bit 8 to 9
P.79
PCI Local Bus Configuration Register Description
The following registers are TP6508 PCI local bus configuration registers. These registers are accessed by first writing the index of the desired register to the Index register, i.e. address Hex CF8 and then accessing the register using the address Hex CFC. Read accesses to reserved (index Hex 0C,0D,0F,18,1C,20,24,28,2C,30,34,38,3E,3F) or unimplemented (index Hex 40 to FF) register can be completed normally and a data value of 0 returned.
Extended Index Register PREG Hex 00 : Vendor ID Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 10D4.
D0-15
Bit 0-15
Vendor ID bit 0 to 15
This field identifies the manufacturer of the device.
Extended Index Register PREG Hex 02 : Device ID Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 860B.
D0-15
Bit 0-15
Device ID bit 0 to 15
This field identifies the particular device. The bit 0 to 4 is as same as the bit of Identification Code in Extended Reg. SREG 05.
Extended Index Register PREG Hex 04 : Command Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 0000.
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10-15
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4
IO space Memory space Bus Master (Reserved =0) Special cycle (Reserved =0) Memory write and invalidate (Reserved =0) VGA palette snoop PERR# enable Wait cycle control (Reserved =0) SERR# enable Fast Back-to-Back Enable (Reserved =0) Reserved =0
Controls TP6508 response to I/O space accesses . A logical 0 disables the device response. A logical 1 allows the device to respond to I/O space accesses . Controls TP6508 response to memory space accesses . A logical 0 disables the device response. A logical 1 allows the device to respond to memory space accesses . Implemented by bus masters only. Controls a device's ability to act as a master on PCI bus. A logical 1 allows the device to behave as a bus master . A logical 0 disables it . Controls a device's action on special cycle operation . This is an enable bit for using the Memory Write and Invalidate command . P.80
Bit 5 Bit 6
Bit 7 Bit 8 Bit 9 Bit 10-15
When this bit is set to logical 1 , special palette snooping behavior is enabled . When this bit is reset to logical 0 , the device should treat palette accesses like all other accesses . This bit controls the device's response to data parity errors. When this bit is set, the devicem u s t take its normal action when a parity error is detected. When this bit is reset, the device must ignore any parity error that it detects and continue normal operation. This bit is used to control whether or not a device does address/data stepping. This bit is an enable bit for the SERR# driver. A logical 1 enables the SERR# driver and report address parity error. A logical 0 disables the SERR# driver. Implemented by bus masters only. Reserved.
Extended Index Register PREG Hex 06 : Status Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 0280.
D0-4 Reserved =0 D5 66 MHz capable (read only =0) D6 UDF support (read only =0) D7 Fast Back-to-Back capable (read only =1) D8 Data Parity Error Detected (reserved =0) D9-10 DEVSEL# timing (read only =01) D11 Signaled Target Abort D12 Received Target Abort (Reserved =0) D13 Received Master Abort (Reserved =0) D14 Signaled System Error D15 Dected Parity Error (A write operation to this register can be reset, but not set.)
Bit Bit Bit Bit 0-4 5 6 7 Reserved. A logical 1 indicates a device is capable of running at 66 MHz. A logical 0 indicates 33 MHz. This optional bit indicates that this device supports User Difinable Features. This optional bit indicates whether or not the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent. Implemented by bus masters only. These bits encode timing of DEVSEL#. There are three allowable timings for asserted of DEVESEL# . They are encoded as binary value 00 for fast , 01 for medium , and 10 for slow . This bit is set by TP6508 whenever its transaction is terminated with target-abort. Implemented by bus masters only. Implemented by bus masters only. This bit must be set whenever the device asserts SERR#. This bit must be set by the device whenever it detects a parity error, even if parity error handing is disabled by bit 6 in the Command register.
Bit 8 Bit 9-10 Bit Bit Bit Bit Bit 11 12 13 14 15
Extended Index Register PREG Hex 08 : Revision ID Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7
Bit 0-7
Revision ID bit 0 to 7
These bits specify TP6508 specific revision identifier. The bit 0 to 2 is as same as the bit of Revision Code of Extended Reg. SREG 05. P.81
Extended Index Register PREG Hex 09 : Prog. Class Code Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Class code bit 0 to 7
Bit 0-7 The class code register is broken into three byte-size field. The upper byte (at offset 0Bh) is a base class code which broadly classifies the type of function the device performs. The middle byte (at offset 0Ah ) is a sub-class code which identifies more specific the function of the device. The lower byte (at offset 09h) identifies a specific register-level programming interface so that device independent software can interact with the device. TP6508 sets the class code of Hex 03,00,00 to mean that is a VGA compatible controller .
Extended Index Register PREG Hex 0A : Sub-Class Code Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Class code bit 8 to 15
Extended Index Register PREG Hex 0B : Base Class Code Register
This is a read only register. Port address is Hex CFC. Default value after hardware reset is Hex 03.
D0-7 Class code bit 16 to 23
Extended Index Register PREG Hex 0C : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved=0
Extended Index Register PREG Hex 0D : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved=0
Extended Index Register PREG Hex 0E : Header Type Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7
Bit 0-7
Header type bit 0 to 7
These bits identify the layout of bytes index 10h through 3Fh in configuration space .
Extended Index Register PREG Hex 0F : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7
Reserved =0
P.82
Extended Index Register PREG Hex 10 : Display Memory Base Address Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 0000,0000.
D0 Display memory space indicator (read-only =0) D1-2 Type select bit 0 to 1 (read-only =00) D3 Prefectchable bit (read-only =0) D4-20 Base address bit 4 to 19 (read-only =0) D21 Base address bit 21 (read-only =0; for 4M-byte display memory) D22-31 Base address bit 22 to 31 (SREG F1 provides the same function for ISA/Local bus only.)
Bit 0 This bit is read-only and used to determine whether the register maps into Memory or I/O space. Base registers that map to Memory space must return a 0 in bit 0 . Base registers that map to I/O space must return a 1 in bit 0. Then , TP6508 set this bit to logical 0 . These bit is read-only . For memory base registers , bit 2 and 1 have an encoded meaning as shown in the following description . Then , TP6508 set these bits to binary logical 00 . Bit 2 Bit 1 Meaning 0 0 Base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space . 0 1 Base register is 32 bits wide Bust must be mapped below 1M in memory space. 1 0 Base register is 64 bits wide and can be mapped anywhere in the 64-bit memory space . 1 1 Reserved. This bit is read-only . TP6508 set this bits to logical 1 and the data is perfectible . There are 4M-byte display memory address space for TP6508 setting. The lower 2MB is for display memory and upper 2MB is for memory mapped IO. Power-up software can determine how much address space TP6508 required by writing a value of all 1's to the register and then reading the value back. When TP6508 has over 1M-byte display memory , it will return 0's in these don't care address bits. By the description of previous bits , the bits 22 through 31 would implement on read and write operation for power-up software determining 4M-byte address space.
Bit 1-2
Bit 3 Bit 4-21
Bit 22-31
Extended Index Register PREG Hex 14 : I/O command Base Address Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 0000,0001. D0 D1 D2-7 D8-31
Bit 0
I/O command space indicator (read-only =1) Reserved =0 Base address bit 2 to 7 (read-only =0) Base address bit 8 to 31
This bit is read-only and used to determine whether the register maps into Memory or I/O space. Base registers that map to Memory space must return a 0 in bit 0 . Base registers that map to I/O space must return a 1 in bit 0. Then , TP6508 set this bit to logical 1 . This bit is reserved , and must return 0 on reads. TP6508 has 256-byte I/O address space . Power-up software can determine how much address space TP6508 required by writing a value of all 1's to the register and then reading the value back . TP6508 will return 0's in these don't care address bits . By the description of previous bits , the bits 8 through 31 would implement on read and write operation for power-up software determining 256-byte address space. P.83
Bit 1 Bit 2-7
Bit 8-31
Extended Index Register PREG Hex 18, 1C, 20, 24, 28, 2C, 30, 34, 38 : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 0000,0000.
D0-31
Reserved =0
Extended Index Register PREG Hex 3C : Interrupt Line Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved =0
Extended Index Register PREG Hex 3D : Interrupt Pin Register
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved =0
Extended Index Register PREG Hex 3E : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved =0
Extended Index Register PREG Hex 3F : Reserved
This is a read/write register. Port address is Hex CFC. Default value after hardware reset is Hex 00.
D0-7 Reserved =0
P.84
Graphics Engine Control Register Description
The following registers with 16-bit data width are Topro VGA Graphics Engine control registers. There are two addressing types, base addressing, and memory map I/O addressing, to access these registers. By base addressing, these registers are accessed at Port binary address xxxx,xxYY,YYYY,YY00. The address value - `Y..' is determined by Graphics Engine Port Address Low Register. They are set default hex. F1 and F3. The high address value - `xx' is determined by following Graphics Engine control register indexed value. Then Topro VGA can access these registers with 16-bit data width by decoding at them, being conjunction with `x..' and `Y..' , directly . By memory map I/O addressing, these registers are accessed as memory command and located at memory address binary ZZZZ,ZZZZ,xxxx,xxYY,YYYY,YY00. The `Y..' and `x..' are as same as the decription of previours paragraph. The address value - `Z..' is determined by Extended registerMemory Mapping I/O Offset Register and it is set default Hex 00. For PCI system access, the GEC. regs. are addressed at by setting PREG 14 and the PCI port address low which is described in the following GEC. register description. The PCI configuration register PREG 14 is used as the higher 8-bit port address and the PCI port address low is defined as the lower 8-bit port address for PCI local bus.
GAREG Hex 01 : Source X Offset Register
This is a read/write register. Default port address 07C4. Default value after hardware reset is Hex 00,00. PCI port address low 04.
D0-10 D11-15
Bit 0-10 Bit 11-15
Source X bit 0 to 10 Reserved
These bits would use to define source X screen position and transfer to memory address for BITBLT operations. Also, these bits are use to define starting X screen position for Line Drawing operations. Reserved .
GAREG Hex 02 : Source Y Offset Register
This is a read/write register. Default port address 0BC4. Default value after hardware reset is Hex 00,00. PCI port address low 08.
D0-10 D11-15
Bit 0-10 Bit 11-15
Source Y bit 0 to 10 Reserved
These bits would use to define source Y screen position and transfer to memory address for BITBLT operations. Also, these bits are use to define starting Y screen position for Line Drawing operations. Reserved .
GAREG Hex 03 : Pattern X Offset Register
This is a read/write register. Default port address 0FC4. Default value after hardware reset is Hex 00,00. PCI port address low 0C.
D0-15
Line drawing pattern bit 0 to 15
P.85
D3-10
Bit 0-15 Bit 3-10
BITBLT pattern X bit 3 to 10
These bits would use to do as the pixel-pattern when Topro VGA is in line drawing command operation. These bits would use to define pattern X screen position and transfer to memory address for BITBLT operations.
GAREG Hex 04 : Pattern Y Offset Register
This is a read/write register. Default port address 13C4. Default value after hardware reset is Hex 00,00. PCI port address low 10.
D0-15 D3-10
Bit 0-15 Bit 3-10
Line drawing pattern bit 16 to 31 BITBLT pattern Y bit 3 to 10
These bits would use to do as the pixel-pattern when Topro VGA is in line drawing command operation. These bits would use to define pattern Y screen position and transfer to memory address for BITBLT operations.
GAREG Hex 05 : Destination X Offset Register
This is a read/write register. Default port address 17C4. Default value after hardware reset is Hex 00,00. PCI port address low 14.
D0-10 D11-15
Bit 0-10 Bit 11-15
BITBLT destination Y bit 0 to 10 Reserved
These bits would use to define destination Y screen position and transfer to memory address for BITBLT operations. Reserved.
GAREG Hex 06 : Destination Y Offset Register
This is a read/write register. Default port address 1BC4. Default value after hardware reset is Hex 00,00. PCI port address low 18.
D0-10 D11-15
Bit 0-10 Bit 11-15
BITBLT destination Y bit 0 to 10 Reserved
These bits would use to define destination Y screen position and transfer to memory address for BITBLT operations. Reserved.
GAREG Hex 07 : X Width & MAX. Term Register
This is a read/write register. Default port address 1FC4. Default value after hardware reset is Hex 00,00. PCI port address low 1C.
D0-10 D11-15
Bit 0-10
Width X bit 0-10 for BITBLT (number of bytes-1 per line) Maxmum term for Line drawing (M) Reserved
These bits would use to define the X direction width of the rectangular region to be copied for BITBLT P.86
operations , and as the value of the maximum term of the caculated equation for the Line Drawong operation. In BILBLK operations, these bits define the X direction width using byte as unit . The caculated equation of the maximum term (M) is :
M = Max ( |X2 -X1| , |Y 2-Y1 | )
Bit 11-15 Reserved .
GAREG Hex 08 : Y Width & Error Term Register
This is a read/write register. Default port address 23C4. Default value after hardware reset is Hex 00,00. PCI port address low 20.
D0-10 D0-12 D13-15
Bit 0-10/12
Width Y bit 0-10 for BITBLT (number of line-1) Error term for Line drawing (E) Reserved
These bits would use to define the Y direction width of the rectangular region to be copied for BITBLT operations , and as the value of the error term of the caculated equation for the Line Drawong operation. In BILBLK operations, these bits define the Y direction width using line as unit . The caculated equation of the error term (E) is :
E = 2 [ Min ( |X2-X1 | , |Y2-Y1 | )-Max ( |X 2-X1 | , |Y2-Y1| ) ]
Bit 13-15 Reserved .
GAREG Hex 09 : Foreground Color Register 1
This is a read/write register. Default port address 27C4. Default value after hardware reset is Hex 00,00. PCI port address low 24.
D0-15
Bit 0-15
Foreground color bit 0 to 15
These bits would use to define the foreground color for rectangular fill, color expansion, and line drawing. Conjunction with foreground color bit 16 to 31,that descripts in GAREG 0A, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. In different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. Another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode.
GAREG Hex 0A : Foreground Color Register 2
This is a read/write register. Default port address 2BC4. Default value after hardware reset is Hex 00,00. PCI port address low 28.
D0-15
Bit 0-15
Foreground color bit 16 to 31
These bits would use to define the foreground color for rectangular fill, color expansion, and line drawing.
GAREG Hex 0B : Background Color Register 1
This is a read/write register. Default port address 2FC4. Default value after hardware reset is Hex 00,00. PCI port address low 2C.
D0-15
Background color bit 0 to 15
P.87
Bit 0-15
These bits would use to define the background color for background fill, color expansion, and line drawing. Conjunction with background color bit 16 to 31,that descripts in GAREG 0C, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. In different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. Another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode.
GAREG Hex 0C : Background Color Register 2
This is a read/write register. Default port address 33C4. Default value after hardware reset is Hex 00,00. PCI port address low 30.
D0-15
Bit 0-15
Background color bit 16 to 31
These bits would use to define the background color for background, color expansion, and line drawing.
GAREG Hex 0D : Transparency Color Register 1
This is a read/write register. Default port address 37C4. Default value after hardware reset is Hex 00,00. PCI port address low 34.
D0-15
Bit 0-15
Transparency color bit 0 to 15
These bits would use to define the transparency color for all graphics engine commands except image read. Conjunction with transparency color bit 16 to 31,that descripts in GAREG 0E, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. In different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. Another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode.
GAREG Hex 0E : Transparency Color Register 2
This is a read/write register. Default port address 3BC4. Default value after hardware reset is Hex 00,00. PCI port address low 38.
D0-15
Bit 0-15
Transparency color bit 16 to 31
These bits would use to define the transparency color all graphics engine commands except image read if transparnecy enabled.
GAREG Hex 0F : Transparency Mask Register 1
This is a read/write register. Default port address 3FC4. Default value after hardware reset is Hex 00,00. PCI port address low 3C.
D0-15
Bit 0-15
Transparency mask bit 0 to 15
These bits would use to define the transparency mask bits that are used to compare with the transparency color all graphics engine commands except image read . Conjunction with transparnecy color bit 16 to 31,that descripts in GAREG 10, we must write with the same color data(byte) into bit 0-7, bit 8-15, bit 16-23, and bit 24-31 for 256-color mode. In different we must write with the same color data(word) into bit 0-15, and bit 16-31 for hi-color mode. Another condiction we use bit 0-23 as color data and reserved bit 24-31 for ture-color mode. The pixels of the destination are compared against the transparency color under control of the transparency mask. Eachbit of transparency mask
P.88
that is a logical 1 makes "Don't care" for the corresponding bit of the transparency color .
GAREG Hex 10 : Transparency Mask Register 2
This is a read/write register. Default port address 43C4. Default value after hardware reset is Hex 00,00. PCI port address low 40.
D0-15
Bit 0-15
Transparency mask bit 16 to 31
These bits would use to define the transparency mask bits that are used to compare with the transparency color all graphics engine commands except image read. The pixels of the destination are compared against the transparency color under control of the transparency mask. Each bit of transparency mask that is a logical 1 makes "Don't care" for the corresponding bit of the transparency color .
GAREG Hex 11 : Top Clipping Position Register
This is a read/write register. Default port address 47C4. Default value after hardware reset is Hex 00,00. PCI port address low 44.
D0-10 D11-15
Bit 0-10 Bit 11-15
Top Clipping position bit 0-10 Reserved
These bits are conjunction with GAREG 12,13,14 to define a rectangular area . Any pixel inside and on the boundary of the rectangular area can be updated during a Graphics Command operation . Reserved
GAREG Hex 12 : Left Clipping Position Register
This is a read/write register. Default port address 4BC4. Default value after hardware reset is Hex 00,00. PCI port address low 48.
D0-10 D11-15
Bit 0-10 Bit 11-15
Left Clipping position bit 0-10 Reserved
These bits are conjunction with GAREG 11,13,14 to define a rectangular area . Any pixel inside and on the boundary of the rectangular area can be updated during a Graphics Command operation . Reserved
GAREG Hex 13 : Bottom Clipping Position Register
This is a read/write register. Default port address 4FC4. Default value after hardware reset is Hex 00,00. PCI port address low 4C.
D0-10 D11-15
Bit 0-10 Bit 11-15
Bottom Clipping position bit 0-10 of bit 0 to 10 Reserved
These bits are conjunction with GAREG 11,12,14 to define a rectangular area . Any pixel inside and on the boundary of the rectangular area can be updated during a Graphics Command operation . Reserved
GAREG Hex 14 : Right Clipping Position Register
This is a read/write register. Default port address 53C4. Default value after hardware reset is Hex 00,00. PCI port address low 50.
P.89
D0-10 D11-15
Bit 0-10 Bit 11-15
Right Clipping position bit 0-10 of bit 0 to 10 Reserved
These bits are conjunction with GAREG 11,12,13 to define a rectangular area . Any pixel inside and on the boundary of the rectangular area can be updated during a Graphics Command operation . Reserved
GAREG Hex 15 : Raster Operation Register
This is a read/write register. Default port address 57C4. Default value after hardware reset is Hex 00,00. PCI port address low 54.
D0-7 D8-10 D11-15
Raster operation code bit 0 to 7 Scan line width selection bits Reserved
Bit 0-7 Raster Operation as defined by Microsoft Windows.All logical operation of Source,Pattern, and Destination data are supported. Bit 8-10 These bit are used to set the scanline offset in pixel unit. Bit-10 Bit-9 Bit-8 Definition 0 0 0 1024 pixels per line 0 0 1 640 pixels per line 0 1 X 800 pixels per line 1 0 0 2048 pixels per line 1 0 1 1280 pixels per line 1 1 X 1600 pixels per line Bit 11-15 Reserved.
GAREG Hex 16 : Graphics Engine Control Register
This is a read/write register. Default port address 5BC4. Default value after hardware reset is Hex 00,00. PCI port address low 58.
D0 D1 D2 D3 D4 D5 D6 D7 D8-9 D10 D11 D12 D13-15
Bit 0 Bit 1 Bit 2
X direction Y direction Source select/Major movement Destination select/Last pixel display enable Graphics function mode select Background transparency enable for color expansion and line drawing Transparency enable Rectangular clipping enable Source format Transparency polarity Rectangular clipping polarity Line drawing pattern width select Reserved
This bit is used to select the direction of X direction. A logical 0 indicates in the increasing direction , and a logical 1 indicates in the decreasing direction. This bit is used to select the direction of Y direction . A logical 0 indicates in the increasing direction , and a logical 1 indicates in the decreasing direction . This bit selects the source as either the screen memory or the host CPU memory for BITBLT operaP.90
Bit 3
Bit 4
Bit 5 Bit 6 Bit 7 Bit 8-9
Bit 10 Bit 11
Bit 12
Bit 13-15
tion. A logical 1 selects Host CPU memory, and a logical 0 select screen memory. Also, it is used to control whether the major movement is in the X or Y direction for Line Drawing operation. A logical 0 indicates in the Y direction(Y>X) , and a logical 1 indicates in the X direction(YY, each bit represent 4 pixel. if XGAREG Hex 20 : Host to Display Data Transfer Register
This is a read/write register. Default port address 83C4. Default value after hardware reset is Hex 00,00,00,00. PCI port address low 80.
D0-31
Data port for image read/write, color expansion
P.91
GAREG Hex 21 : Hardware Cursor Pattern Start Address Register
This is a read/write register. Default port address 87C4. Default value after hardware reset is Hex 00,00. PCI port address low 84.
D0-15
Bit 0-15
Memory address A6 to A21 for hardware cursor pattern
These bits would use to define the location in the display memory where the cursor pattern is stored . The cursor pattern may be stored anywhere in the display memory but is generally stored in a nonvisible location (off-screen memory ) . We can set the line offset of hardware cursor pattern in GAREG 26 bit-14 . Others , the start address of hardware cursor pattern has an address-alignment limit as follows : 1) If GAREG 26 bit-14 = 0 ( line offset = 16 bytes ) , then the start address of hardware cursor pattern must be 1k-byte alignment . It is easy to fill hardware cursor pattern data contiuously . This register bit-mapping of memory address is : ( x : no used ) D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,D10,D11,D12,D13,D14,D15 == x , x , x , x ,A10,A11,A12,A13,A14,A15,A16,A17,A18,A19,A20,A21 2) If GAREG 26 bit-14 = 1 ( line offset = 2048 bytes ) , then the start address of hardware cursor pattern can be 64-byte alignment in the first 2048-byte memory address (A6-A10) of any 64x2048-byte memory segment (A17-A21) . It is useful for 1280x or 1600x display mode . This register bit-mapping of memory address is : ( x : no used ) D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,D10,D11,D12,D13,D14,D15 == A6 ,A7 ,A8 ,A9 ,A10, x , x , x , x , x , x ,A17,A18,A19,A20,A21
GAREG Hex 22 : Hardware Cursor X&Y Origin Register
This is a read/write register. Default port address 8BC4. Default value after hardware reset is Hex 00,00. PCI port address low 88.
D0-5 D6-7 D8-13 D14-15
Bit 0-5
Hardware cursor X-size Xbit 0-5 Reserved Hardware cursor Y-size Ybit 0-5 Reserved
Bit 6-7 Bit 8-13
Bit 14-15
These bits would use to define the X offset in pixels from the left edge of the pattern which will be displayed at the cursor display position . D0 ,D1 ,D2 ,D3 ,D4 ,D5 ==XO0,XO1,XO2,XO3,XO4,XO5 Reserved These bits would use to define the Y offset in pixels from the top edge of the pattern which will be displayed at the cursor display position . D8 ,D9 , D10,D11 ,D12 ,D13 ==YO0,YO1,YO2,YO3,YO4,YO5 Reserved
GAREG Hex 23 : Hardware Cursor X Display Position Register
This is a read/write register. Default port address 8FC4. Default value after hardware reset is Hex 00,00. PCI port address low 8C.
D0-7 D8-10 D11-15
Hardware cursor display X position bit 0-7 Hardware cursor display X position bit 8-10 Reserved
P.92
Bit 0-10
Bit 11-15
These bits would use to define the X location on the screen at which the cursor origin is displayed . These values represent a position in pixels , referenced to the left edge of the screen . D0, D1, D2 , D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,D10 == XP0,XP1,XP2,XP3,XP4,XP5,XP6,XP7,XP8,XP9,XP10 Reserved
GAREG Hex 24 : Hardware Cursor Y Display Position Register
This is a read/write register. Default port address 93C4. Default value after hardware reset is Hex 00,00. PCI port address low 90.
D0-7 D8-10 D11-15
Bit 0-10
Hardware cursor display Y position bit 0-7 Hardware cursor display Y position bit 8-10 Reserved
Bit 11-15
These bits would use to define the Y location on the screen at which the cursor origin is displayed . These values represent a position in pixels , referenced to the top edge of the screen . D0 ,D1 ,D2 ,D3 ,D4 ,D5 ,D6 ,D7 ,D8 ,D9 ,D10 == YP0,YP1,YP2,YP3,YP4,YP5,YP6,YP7,YP8,YP9,YP10 Reserved
GAREG Hex 25 : Hardware Cursor Primary Color Register 1
This is a read/write register. Default port address 97C4. Default value after hardware reset is Hex 00,00. PCI port address low 94.
D0-7 D8-15
Bit 0-7 Bit 8-15
Hardware cursor primary color bit 0 to 7 for 8 bit color mode Hardware cursor primary color bit 8 to 15 for 16 bit color mode
These bits would use to define the primary color of hardware cursor for 8 bit color mode. These bits would use to define the primary color of hardware cursor for 16 bit color mode.
GAREG Hex 26 : Hardware Cursor Primary Color Register 2
This is a read/write register. Default port address 97C4. Default value after hardware reset is Hex 00,00. PCI port address low 98.
D0-7 D8-13 D14 D15
Bit 0-7 Bit 8-13 Bit 14
Hardware cursor primary color bit 16 to 23 for 24 bit color mode Reserved Hardware cursor pattern address line offset selection Enable hardware cursor
These bits would use to define the primary color of hardware cursor for 24 bit color mode. Reserved This bit is used to select memory line offset of hardware cursor pattern. 0: 16-byte 1: 2048-byte A logical 1 enables Topro VGA's Hardware Cursor function in operation . A logical 0 disables it. The data definition of hardware cursor pattern list in following description .
Bit 15
P.93
Data bit-1 0 0 1 1
Data bit-0 0 1 0 1
Definition Hardware cursor Primary color Hardware cursor Secondary color Transparent Inversion or hardware cursor auxiliary color (decided by GAREG 2A bit-15 selection)
GAREG Hex 27 : Hardware Cursor Secondary Color Register 1
This is a read/write register. Default port address 9FC4. Default value after hardware reset is Hex 00,00. PCI port address low 9C.
D0-7 D8-15
Bit 0-7 Bit 8-15
Hardware cursor secondary color bit 0 to 7 for 8 bit color mode Hardware cursor secondary color bit 8 to 15 for 16 bit color mode
These bits would use to define the secondary color of hardware cursor for 8 bit color mode. These bits would use to define the secondary color of hardware cursor for 16 bit color mode.
GAREG Hex 28 : Hardware Cursor Secondary Color Register 2
This is a read/write register. Default port address A3C4. Default value after hardware reset is Hex 00,00. PCI port address low A0.
D0-7 D8-14 D15
Bit 0-7 Bit 8-14 Bit 15
Hardware cursor secondary color bit 16 to 23 for 24 bit color mode Reserved Exchange primary color and secondary color
These bits would use to define the secondary color of hardware cursor for 24 bit color mode. Reserved. A logical 1 forces the hardware cursor display color to be Reverse . The Hardware cursor Primary color and Secondary color are changed each other in the data definition description of GAREG 26 by bit-15. A logical 0 disables it .
GAREG Hex 29 : Hardware Cursor Auxiliary Color Register 1
This is a read/write register. Default port address A7C4. Default value after hardware reset is Hex 00,00. PCI port address low A4.
D0-7 D8-15
Bit 0-7 Bit 8-15
Hardware cursor auxiliary color bit 0 to 7 for 8 bit color mode Hardware cursor auxiliary color bit 8 to 15 for 16 bit color mode
These bits would use to define the auxiliary color of hardware cursor for 8 bit color mode. These bits would use to define the auxiliary color of hardware cursor for 16 bit color mode.
GAREG Hex 2A : Hardware Cursor Auxiliary Color Register 2
This is a read/write register. Default port address ABC4. Default value after hardware reset is Hex 00,00. PCI port address low A8.
D0-7 D8-14 D15
Hardware cursor auxiliary color bit 16 to 23 for 24 bit color mode Reserved Enable three color mode
P.94
Bit 0-7 Bit 8-14 Bit 15
These bits would use to define the auxiliary color of hardware cursor for 24 bit color mode. Reserved This bit is used to select Hardware Cursor display color mode . A logical 0 indicates Topro VGA is operated in two color mode . A logical 1 forces Topro VGA is operated in three color mode by using cursor Auxiliary color to replace inversion destination data color.
GAREG Hex 2B : Graphics Command FIFO Status Register
This is a read/write register. Default port address AFC4. Default value after hardware reset is Hex 00,00. PCI port address low AC.
D0 Graphics command access status D1 Host memory from Display memory write status D2 Host memory to Display memory read status D3 Command FIFO empty status D4 Command FIFO full status D5-7 Video line buffer valid status D8-15 Command FIFO valid status (*: Write access operation will reset graphic engine)
Bit 0 This bit reflects the access status of Graphics commands . A logical 1 indicates Topro VGA is excuting the Graphics command in busy ststus now . A logical 0 indicates Topro VGA has excuted the Graphics command. This bit reflects the write access status of Host memory to Display memory . A logical 1 indicates Topro VGA is busy now . This bit reflects the read access status of Host memory from Display memory . A logical 1 indicates Topro VGA is busy now . This bit reflects the command FIFO empty status . A logical 0 indicates the command FIFO is empty now . A logical 1 indicates the command FIFO isn't empty . This bit reflects the command FIFO full status . A logical 0 indicates the command FIFO isn't full . A logical 1 indicates the command FIFO is full now . These bits reflects the video line buffer vaild status as following description . Bit-7 Bit-6 Bit-5 Status description 0 0 0 Video line buffer empty blocks < 4 (32-bits data/1 block) 0 0 1 Video line buffer empty blocks >= 4 0 1 1 Video line buffer empty blocks >= 8 1 1 1 Video line buffer empty blocks >= 16 These bits reflects the command FIFO vaild status as following description . Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit 8 Status description 1 1 1 1 1 1 1 1 0 empty FIFO is available (Full) 0 1 1 1 1 1 1 1 1 empty FIFO is available 0 0 1 1 1 1 1 1 2 empty FIFO is available 0 0 0 1 1 1 1 1 3 empty FIFO is available 0 0 0 0 1 1 1 1 4 empty FIFO is available 0 0 0 0 0 1 1 1 5 empty FIFO is available 0 0 0 0 0 0 1 1 6 empty FIFO is available 0 0 0 0 0 0 0 1 7 empty FIFO is available 0 0 0 0 0 0 0 0 8 empty FIFO is available (Empty)
Bit 1 Bit 2 Bit 3 Bit 4 Bit 5-7
Bit 8-15
P.95
VIII. Absolute Maximum Rating
Storage temperature Ambient temperature under bias Voltage on any pin with respect to ground Active mode power dissipation Power supply voltage -40 to +125 degree c 0 to +70 degree c GND-0.5 to VCC +0.5V 1.8 Watts 7 Volts
P96
IX. DC Electrical Characteristic
DC Characteristics
Symbol Parameter VCC VIL VIH Vt+ VtVOL VOH Icc0 Icc1 Icc2 Icc3 Icc4 IIL IOTL CIN COUT Power Supply (+5.0V) Power Supply (+3.3V) Input Low Voltage Input High Voltage
Low to High Threshold Voltage High to Low Threshold Voltage
Min 4.75 3 -0.5 2 1.5 2.4 2.4 -10 -10 -
Typ 5 3.3 -
Max 5.25 3.6 0.8
VCC+0.5
Unit Conditions V Normal Operation V Normal Operation V VCC=5.0+-5% (a) V VCC=5.0+-5% V Schmitt Trigger(preset) (h) V Schmitt Trigger(preset) (h) V IOL=+12mA (b) V IOL=+12mA (b) V IOH=-12mA (b) V IOH=-12mA (b) mA On power mode (c) mA On power mode (d) mA Standby/Suspend mode (e) mA Off power mode (f) mA Cover close mode (g) uA VSS3.5 0.4 0.4 320 150 32 18 165 10 10 10 10
Output Low Voltaget (5.0V) Output Low Voltage (3.3V) Output High Voltage (5.0V) Output High Voltage (3.3V) Operating Current (5.0V) Operating Current (3.3V) Operating Current Operating Current Operating Current (5.0V) Input Leakage Current Output Tri-state Leakage Input Capacitance Output Capactance
(a) RESET pin is CMOS level (b) See the DC Drive Characteristics on the next table (c) VCLK = 25.175 MHz , MCLK = 55 MHz (CRT-PANEL Dual display) VCLK = 129.400 MHz , MCLK = 60 MHz (CRT only display) (d) VCLK = 65 MHz , MCLK = 55 MHz (CRT only display) (e) VCLK = 0, MCLK = 7 MHz (CRT-PANEL Dual display) (f) VCLK = 0 , MCLK = DRAMs refresh frequency 32KHz (CRT-PANEL Dual display) (g) VCLK = 25.175 MHz , MCLK = 55 MHz (h) Test voltage level range : +/- 200mv [85.12.09 508DC.TBL] P97
DC Drive Characteristics
Symbol Parameter Output Pins LRDY#,LDEV#,HSYNC,VSYNC IOL SHFCLK,FPVCC,FPVEE,FPBACK Output Low Drive D[31:0],A[27:24],OEAB* LP,FLM,M,P[23:0] All other output pins LRDY#,LDEV#,HSYNC,VSYNC SHFCLK,FPVCC,FPVEE,FPBACK IOH Output High Drive D[31:0],A[27:24],OEAB* LP,FLM,M,P[23:0] All other output pins
Operating voltage is 4.75v for 5V operation and 3.3v for 3.3V operation. [85.02.09 508DC2.TBL]
Min Unit Conditions 12 8 4 12 8 4 mA Output voltage=VOL mA Output voltage=VOL mA Output voltage=VOL mA Output voltage=VOH mA Output voltage=VOH mA Output voltage=VOH
DAC Characteristics
Symbol Parameter Vo Io Output voltage Output Current DAC Resolution Full Scale Error DAC to DAC Cross-talk DAC Linearity Full Scale settling Time Output Rise/Fall Time Comparator Sensitivity 50 +/-2 15 6 Min Typ 1 20 30 8 +/-5 TBD Max Unit Conditions V Io< 20mA
mA Vo< 1.0v, 37.5ohm load Bits % % LSB ns ns mV 10% to 90%
Operating voltage is 5.0v for 5V operation and 3.3v for 3.3V operation.
[85.02.09
508DC3.TBL]
P98
X. AC Electrical Characteristic
AC Testing VIH / VIL : 5.0/0.0 Volt VOH / VOL : 2.0/0.8 Volt ( VCLK = 28.322MHZ / MCLK = 55MHz ) " Non-100% test "
BIOS ROM Interface Timing SPEC.
Symbol T1 T2 T3 T4 T5 T6 T7 Parameter Description SA0-19 setup time to SMEMR* SA0-19 hold time to SMEMR* SMEMR* pulse low width SMEMR* asserted to SD floated delay SD floated delay from SMEMR* negated Delay time from SMEMR* low to ROMCS* low Delay time from SMEMR* high to ROMCS* high [84.06.26 MIN. 20 150 150 20 60 40 40 MAX. Units ns ns ns ns ns ns ns
SP508T01.TBL]
P99
ISA Bus Interface Timing SPEC.
Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 Parameter Description SBHE*,SA[16:0] to COMMAND ( SMEMR*, SMEMW*, IORD*, IOWR* ) low setup time SBHE*,SA[16:0] to COMMAND low hold time LA[23:17] to COMMAND low setup time LA[23:17] to COMMAND high hold time SD[15:0] write data to IOWR*/MEMW* high setup time SD[15:0] read/write data/ to COMMAND high hold time IORD* pulse low width IOWR* pulse low width SD[15:0] read data valid after IORD* low IORDY* high from SMEMR* low SD[15:0] read data valid from IORDY* high OWS low from IORD* , SMEMR* low IORDY* low from COMMAND low SA[16:0] valid to IOCS16* low IOCS16* from IOW* high hold time LA[23:17] valid to MEMCS16* MEMCS16* tristate from the next active ALE AEN to IORD* , IOWR* low setup time AEN from IORD* , IOWR* high setup time REF* to SMEMR* low setup time REF* from SMEMR* high hold time 5 5 20 0 [84.06.26 10 10 MIN. 18 10 20 10 20 10 70 40 70 2.45us 40 15 25 35 20 41 39 MAX. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SP508T02.TBL]
P100
PCI Local Bus Interface Timing SPEC.
Symbol T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22 T23 Parameter Description FRAME# setup time to CLK high FRAME# hold time from CLK high Address setup time to CLK high Address hold time from CLK high Read data activ delay from CLK high Read data hold time from CLK high Command setup time to CLK high Command hold time from CLK high BE[3:0] setup time to CLK high BE[3:0] hold time from CLK high IRDY# setup time to CLK high IRDY# hold time from CLK high DEVSEL# low delay from CLK high DEVSEL# high delay from CLK high DEVSEL# tristate delay from CLK high TRDY# low delay from CLK high TRDY# high delay from CLK high TRDY# tristate delay from CLK high STOP# low delay from CLK high STOP# high delay from CLK high STOP# tristate delay from CLK high PAR setup time to CLK high PAR time from CLK high 3.1 [84.06.26 3.6 3.9 4 3.6 3.8 3.5 4.1 2 0.8 1.3 2 3 0.3 14.4 12.1 11.5 15.4 12.7 11 19.3 11.8 12.7 10.4 10.4 MIN. 5.1 3.7 4.9 1.6 25 MAX. Units ns ns ns ns ns ns ns
ns
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
SP508T12.TBL]
P101
Memory Bus Interface Timing SPEC.
MCLK Frequency = 56 MHz Symbol Tm Th Tl T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 MCLK period MCLK high pulse MCLK low pulse RAS precharge time (16-bit CPU/GFX CRT cycle) RAS pulse width (16-bit CPU/GFX CRT cycle) RAS to CAS delay time CAS pluse width CAS percharge time ROW address setup time ROW address hold time COLUMN address setup time COLUMN address hold time Access time from RAS Random Read/Write cycle time Fast Page mode cycle time Access time from OE* low Output disable time after OE* low Wite command setup time Wite command hold time Write command pulse width RAS pulse width Random Read/Write cycle time Parameter Description MIN. 17.86 8.93+/-5% 8.93+/-5% 3 6 3 1.5 0.5 1 2 1 1 3.75 9 2 1.75 0.75 1 1.5 4.5 4 7 [84.06.26 MAX. Units ns ns ns Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm SP508T05.TBL]
P102
Memory Interface Timing SPEC.
(Continuance)
Symbol T20 T21 T22 T23 T24 T25 T26 T27 T28 T29 T30 T31 T32 T33 T34 Parameter Description Read-modify-Write RAS pulse width Read-modify-Write Random Read/Write cycle time (16-bit) Read-modify-Write RAS to CAS delay time Read-modify-Write CAS pluse width Read-modify-Write CAS percharge time Read-modify-Write Fast Page mode cycle time Read-modify-Write COLUMN address hold time Read-modify-Write Date-In setup time Read-modify-Write Date-In hold time Read-modify-Write Write command pulse width Read-modify-Write OE* command pulse width Read-modify-Write Access time from OE* low Read-modify-Write Output disable time after OE* low Read-modify-Write RAS pulse width Read-modify-Write Random Read/Write cycle time (32-bit) MIN. 12 15 3 1.5 0.5 2 4 0.5 1 2.5 2.5 1.25 0.25 7 10 1.5 3 MAX. Units Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm Tm
[84.06.26
SP508T14.TBL]
P103
RAMDAC & Feature Connector Interface Timing
PCLK frequency: 110 MHz
Symbol T1 T2 T3 T4 T5 T6 T7 Parameter Description Pixel clock cycle time Pixel clock pulse width high time Pixel clock pulse width low time VP[23:0],HSYNC,VSYNC,BLANK* setup time VP[23:0],HSYNC,VSYNC,BLANK* hold time Analog output delay Analog output skew [84.06.26 MIN. 9.1 3.5 3.5 3 3 30 2 MAX. Units ns ns ns ns ns ns ns
SP508T13.TBL]
Color-Key PC Video & VAFC Interface Timing
Symbol Tvclk T1 T2 T3 T4 T5 T6 Parameter Description VCLK Input frequency VCLK Input clock High time VCLK Input clock Low time PC Video input data to PCLK setup time PC Video input data from PCLK hold time VAFC input data to PCLK setup time VAFC input data from PCLK hold time MIN. 10 10 12 0 10 2 [84.08.28 MAX. 37.5 Units MHz ns ns ns ns ns ns
SP508T16.TBL]
P104
XI. Timing Diagrams
BIOS ROM Read Cycle
T1 T2
SA [19 :0 ]
V alid A ddress
T3
SM E M R *
T4 T5
SD [7:0 ]
T6 T7
ROMCS* (EPROM *)
SP50 8E0 1 .D RW 8 4 /0
P105
ISA Bus Interface Timing
SA [16:0] SB HE*
T1
V aild
T2
A LE
T3 T4
LA [23:17]
V aild
T5 T6
V aild
SD [15:0]
T7 T8
D ata
IO RD * IO W R*
T9 T 10 T 11
SM EM R* SM EM W *
T 12
O W S*
T 13
IO RD Y* IO CS16 *
H I-Z
T 14 T 15
H I-Z H I-Z
T 16
H I-Z
T 17
H I-Z M EM CS16*
T 18 T 19
H I-Z
A EN
T 20 T 21
R EF*
S P 50 8 E0 2.D R W 8 4 /0
P106
PCI Local Bus Interface Timing (32-bit data bus)
CLK
T1 T2
FRAME#
T3 T4
[W R IT E ]
A D [3 1 :0 ] A [3 1 :0 ] D [3 1 :0 ]
T5 T6
[R E A D ]
A D [3 1 :0 ] A [3 1 :0 ]
T7 T8 T9
D [3 1 :0 ]
T10
C /B E [3 :0 ]#
CM D
T11
B E [3 :0 ]#
T12
IR D Y #
T13 T14 T15
H i-Z D E V SE L # H i-Z
T16 T17 T18
H i-Z TRDY#
T19 T20 T21
H i-Z
H i-Z STOP#
T22 T23
H i-Z
PAR
V a lid
V a lid
S P50 8E0 5.D R W 8 4/06/
P107
16-Bit TXT CRT Cycle
State
T0
S0 S0 S1
T1
S2 S3
T 2*
S0 S1
T0
S0 S0 S1
T1
S2 S3 S0
T 2*
S1
T 0*
S0
M CLK
T 19 T1 T 18
R ASA *
T3 T4
C ASA L* C ASA H* (CASA *) QA0 ROW
T6 T7 T 10
A SC A TR
CG CG'
MA
COL
T8 T9
C G RO W
C G CO L
M AD[7:0] M AD[15:8]
M AP0 A SC M AP1 A TR
M AP2 CG M AP3 CG'
W EA* (W EA L*,W EA H*) O EA B* ROW A SCLH A TR LH R LH3-0 FIFO LH EX TFIFO LH
S P 50 8 E0 6.D R W 8 4/0
P108
16-Bit CPU/GFX CRT/Shadow Frame Buffer Cycle
State
T0
S0 S0
T1
S1 S2 S3 S0
T2*
S1 S0
T3*
S1
T0*
S0
MCLK
T11 T1 T2
RASA*
T12 T3 T4 T5
CASAL* CASAH* (CASA*) QA0 MA
T6
MAP0 MAP1
MAP2 MAP3
ROW
T7
COL
T8 T10 T9
COL+1
[Read Cycle]
MAD[7:0] MAD[15:8] WEA*
WEAL*,WEAH*
MAP0 MAP1
T13
MAP2 MAP3
T14
OEAB*
[Write Cycle]
MD[7:0] MD[15:8]
T15 T17
MAP0 MAP1
MAP2 MAP3
T16
WEA*
(WEAL*,WEAH*)
OEAB* ROW FIFOLH
CPULH
[SP508E07.DRW 84/06/19]
P109
32-Bit TXT CRT Cycle
State
T0
S0 S0 S1
T1
S2 S3
T2*
S0 S1
T0
S0 S0 S1
T1
S2 S3 S0
T2*
S1
T0*
S0
MCLK
T19 T1 T18
RASA*
T3 T4
CASAL* CASAH* (CASA*) RASB* CASBL* CASBH* (CASB*)
MA
ASC ATR
ASC/ATR
CG CG' ROW
T6 T7 T10
COL
T8 T9
CG ROW
CG COL
MAD[7:0] MAD[15:8] MBD[7:0] MBD[15:8]
MAP0 ASC MAP1 ATR MAP2 CG MAP3 CG'
WEA* (WEAL*,WEAH*) WEB* (WEBL*,WEBH*) OEAB*
[SP508E08.DRW 84/06/19
P110
32-Bit CPU/GFX CRT/Shadow Frame Buffer Cycle
State
T0
S0 S0 S1
T1
S2 S3
T2*
S0 S1
T0*
S0 S0 S1
T1
S2 S3 S0
T2*
S1
T0*
S0
MCLK
T1
T19
T18
RASA*
T3 T4
CASAL*
CASAH* RASB*
(CASA*)
MAP0 MAP1
CASBL*
CASBH* (CASB*)
MAP2 MAP3
MA
T6
ROW
T7 T10
COL
T8 T9
[Read cycle]
MAD[7:0] MAD[15:8] MBD[7:0] MBD[15:8] OEAB*
MAP0 MAP1 MAP2 MAP3
[Write cycle]
MAD[7:0] MAD[15:8] MBD[7:0] MBD[15:8] WEA* (WEAL*,WEAH*) WEB*
(WEBL*,WEBH*)
[SP508E09.DRW 84/06/19]
MAP0 MAP1 MAP2
MAP3
P111
16-Bit Read-Modify-Write Cycle
State T0 T1
T4 T5
T0*
S0
S0
S1
S2
S3
S0
T21
S1
S2
S3
S4
S0
S1
S2
S3
S4
S0
MCLK
T1
T20
RASA*
[Dual-CAS]
CASAL* CASAH* WEA*
T25
T22
T23
T24
MAP0 MAP1
MAP0 MAP1
T29
MAP2 MAP3
MAP2 MAP3
[Dual-WE]
CASA* WEAL* WEAH* MA
T6
ROW
T7 T10 T8
COL
T26 T27 T28
COL+1
MAD[7:0] MAD[15:8]
MAP0/R MAP1/R
MAP0/W MAP1/W
T30 T31
MAP2/R MAP3/R
MAP2/W MAP3/W
T32
OEAB* QA0
[SP508E10.DRW 84/06/19]
P112
32-Bit Read-Modify-Write Cycle
S ta te T0 T1
T4
T 0*
S0
S0
S1
S2
S3
S0
S1
S2
S3
S4
S0
M CLK
T1
T 34 T 33
R ASA *
[D ual-C A S]
C ASA L* C ASA H* C ASB L* C ASB H* W EA*/W EB *
T 22
T 23
M AP0 M AP1 M AP2 M AP3
M AP0 M AP1 M AP2 M AP3
[D ual-W E ]
C ASA */CA SB* W EAL*/W EB L* W EAH */W EBH* MA
T6
RO W
T7 T8
CO L
T 26 T 27 T 28
T 10
M AD[7:0] M AD[15:8] M AD[7:0] M AD[15:8]
M A P0 /R M A P1 /R
M A P0 /W M A P1 /W
M A P2 /R M A P3 /R
M A P2 /W M A P3 /W
T 32
O EA B*
SP508E11.DRW 84/06
P113
Refresh Cycle Cycle(CAS Before RAS)
State
T0
S0 S0 S1
T1
S2 S3 S0
T2
S1
T 0*
S0
M C LK
T 19 T1 T 18
RA SA* RA SB* RA SC*
[D U A L-CA S ]
C A S A L *,C A S A H * C A S B L *,C A S B H* C A S C L *,C A S C H* W E A *,W E B *,W E C *
[D U A L-W R IT E]
C A S A *,C A S B *,C A S C * W E A L *,W E A H * W E B L *,W E B H * W E C L *,W E C H *
O E A B *,O E C *
S P 50 8 E1 5.D R W 8 4 /0
P114
External Frame Buffer Interface Timing (16-bit)
S ta te T0 T1
T2
T 0*
S0
S0
S1
S0
S1
S2
S3
S4
S5
S6
S7
S8
S9
S 1 0 S 1 1 S 12 S 13 S 14 S 1 5 S 0
S0
S0
M CLK
T 11 T1 T2
R ASC *
T4
[D ual-C A S]
C ASC L* C ASC H*
T3
T5
T 12
T 13
W EC*
[D ual-W E ]
C ASC * W ECL* W ECH * ROW
T6 T7
T 10 T8
CA
COL
CO L+1
T9
CO L+2
[R e ad C yc le]
M CD[15:0 ]
R GB
R GB
R GB
[W rite C ycle]
M CD[15:0 ]
R GB R GB
T 14
R GB
O EC *
SP508E16.DRW 84/06
P115
RAMDAC & Feature Connector Interface Timing
T1
T2
T3
PCLK HSYNC VSYNC BLANK* VP[7:0] R[7:0],G[7:0],B[7:0] PSEUDO COLOR 16-BIT COLOR 24-BIT COLOR
T6
T4 T4 T5
T5
PIXEL 1
PIXEL 2
PIXEL 3
RED GREEN
T7
BLUE
[SP508E18.DRW 84/06/2
P116
Color-Key PC Video & VAFC Interface Timing
T1
T2
(Color-key PC Video) PCLK out (VAFC interface) VCLK in
T3 T5
T4 T6 PIXEL 2 PIXEL 3
(Color-key PC Video) VR[7:0],VG[7:0],VB[7:0] (VAFC interface) VP[15:0] (VAFC interface) GRDY (VAFC interface) VRDY (VAFC interface) ENVID#
PIXEL 1
High High
[SP508E17.DRW 84/08/29]
P117
XII. Appendix
A. Monitor Specification
* Super VGA Display Monitor Spec. Mode IBM 320x , 640x IBM 360x , 720x TXT 132x25(Font 8x16,8x14) TXT 132x44(Font 8x8) 640x400 640x480 800x600 1024x768 /Interlaced 1024x768 /Non-Interlaced 1280x1024 /Interlaced 1280x1024 /Non-Interlaced 1600x1280 /Interlaced VCLK 25.175MHz 28.322MHz 40MHz 40MHz 25.175MHz 25.175MHz 36MHz 44.9MHz 65MHz 75MHz 102.4MHz 108MHz HSYNC 31.5KHz 31.5KHz 31.5KHz 31.5KHz 31.5KHz 31.5KHz 35.156KHz 35.52KHz 48.363KHz 46.875KHz 64KHz 57.447KHz VSYNC 70Hz 70Hz 60Hz 70Hz 70Hz 60Hz 56.25Hz 87Hz 60Hz 87Hz 60Hz 87Hz
* VESA VGA Display Monitor Spec Mode IBM 320x , 640x IBM 360x , 720x 640x400 640x480 640x480 800x600 800x600 800x600 1024x768 /Non-Interlaced 1024x768 /Non-Interlaced 1024x768 /Non-Interlaced 1280x1024 /Non-Interlaced VCLK 31.5MHz 31.5MHz 31.5MHz 31.5MHz 31.5MHz 40MHz 50MHz 49.5MHz 65MHz 75MHz 78.75MHz 135MHz HSYNC 37.86KHz 37.86KHz 37.86KHz 37.86KHz 37.5KHz 37.879KHz 48.077KHz 46.875KHz 48.363KHz 56.476KHz 60.023KHz 79.976KHz VSYNC 84Hz 84Hz 84Hz 72.8Hz 75Hz 60.3Hz 72.2Hz 75Hz 60Hz 70Hz 70Hz 75Hz
P118
B. TP6508 VGA Modes
TP6508 VGA Modes
Mode
Display Size 320x200 320x350 360x400 640x200 640x350 720x400 320x200 640x200 720x350 720x400 320x200 640x200 640x350 640x350 640x480 640x480 320x200 1056x400 1056x396 1056x400 1600x1280/I 1600x1280/ 1600x1280/I 1600x1280/ 1600x1280/ 800x600 1024x768/I 1024x768/N 640x200 640x400 640x480 800x600 1024x768/I 1024x768/N
Type A/N A/N A/N A/N A/N A/N APA APA A/N A/N APA APA APA APA APA APA APA A/N A/N A/N APA APA APA APA APA APA APA APA APA APA APA APA APA APA
Colors /Shades 16/256K 16/256K 16/256K 16/256K 16/256K 16/256K 4/256K 2/256K Mono Mono 16/256K 16/256K Mono 16/256K 2/256K 16/256K 256/256 16/256K 16/256K 16/256K 256/256 256/256 65536 65536 16/256K 16/256K 16/256K 16/256K 256/256 256/256 256/256 256/256 256/256 256/256
Alpha Format 40X25 40X25 40X25 80X25 80X25 80X25 40X25 80X25 80X25 80X25 40X25 80X25 80X25 80X25 80X30 80X30 40X25 132X25 132X44 132X25 200X80 200X80 200X80 200X80 200X80 100X37 128X48 128X48 80X25 80X25 80X30 100X37 128X48 128X48
Buff Start B80 B80 B80 B80 B80 B80 B80 B80 B00 B00 A00 A00 A00 A00 A00 A00 A00 B80 B80 B80 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00
Box Size 8X8 8X14 9X16 8X8 8X14 9X16 8X8 8X8 9X14 9X16 8X8 8X8 8X14 8X14 8X16 8X16 8X8 8X16 8X8 8X14 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16
VCLK (MHz)
HSync (KHz)
VSync (Hz)
Min. Memory Size
Max. Page
0/1 0*/1* 0+/1 2/3 2*/3* 2+/3 4/5 6 7 7+ D E F 10 11 12 13 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30
25.17 25.17 28.32 25.17 25.17 28.32 25.17 25.17 28.32 28.32 25.17 25.17 25.17 25.17 25.17 25.17 25.17 40 40 40 108 166.6 108 166.6 166.6 36 44.9 65 25.17 25.17 25.17 36 44.9 65
31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 31.5 30.9 30.9 30.9 57.44 79.2 57.44 79.2 79.2 35.5 35.5 48.36 31.5 31.5 31.5 35.5 35.5 48.36
70 70 70 70 70 70 70 70 70 70 70 70 70 70 60 60 70 60 70 70 87 60 87 60 60 57 87 60 70 70 60 57 87 60
[88.04.12
256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 256KB 2MB 2MB 4MB 4MB 1MB 256KB 512KB 512KB 512KB 512KB 512KB 512KB 1MB 1MB
8 8 8 8 8 8 1 1 8 8 8 4 2 2 1 1 1 4 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1
TPMODE1.TBL]
P119
TP6508 VGA Modes
(Continuous)
Mode
Display Size 1280x1024/I 1280x1024/ 1280x1024/I 1280x1024/ 1280x1024/I 1280x1024/ 1600x1280/I 640x480 800x600 640x480 800x600 1024x768/I 1024x768/N 1024x768/I 1024x768/N 1280x1024/I 1280x1024/
Typ APA APA APA APA APA APA APA APA APA APA APA APA APA APA APA APA APA
Colors /Shades 1677721 1677721 16/256K 16/256K 256/256 256/256 16/256K 65536 65536 1677721 1677721 65536 65536 1677721 1677721 65536 65536
Alpha Format 160X64 160X64 160X64 160X64 160X64 160X64 200X80 80X30 100X37 80X30 100X37 128X48 128X48 128X48 128X48 160X64 160X64
Buff Start A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00 A00
Box Size 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16 8X16
VCLK (MHz)
HSync (KHz)
VSync (Hz)
Min. Max. Memory Page size
31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41
75 102.4 75 135 75 102.4 129.4 25.17 36 25.17 36 44.9 65 44.9 65 75 102.4
46.87 64 46.87 79.97 46.87 64 64.7 31.5 35.5 31.5 35.5 35.5 48.36 35.5 48.36 46.87 64
87 60 87 75 87 60 96 60 56.25 60 56.25 87 60 87 60 87 60
[88.04.12
4MB 4MB 1MB 1MB 2MB 2MB 1MB 1MB 1MB 1MB 2MB 2MB 2MB 4MB 4MB 4MB 4MB
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
TPVGAM2.TBL]
: TP6508 don't support mode 23 , 24 , 25 , 26 , 27 , 3E , 3F , 40 , 41 .
P120
C. Rast Operation Code List
a : and o : or x : xor n : not Boolean function : in R Polish in HEX
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 0 DPSoon DPSona PSon SDPona DPon PDSxnon PDSaon SDPnaa PDSxon DPna PSDnaon SPna PDSnaon PDSonon Pn PDSona DSon SDPxnon SDPaon DPSxnon DPSaon PSDPSanaxx SSPxDSxaxn SPxPDxa SDPSanaxn PDSPaox SDPSxaxn PSDPaox DSPDxaxn PDSox PDSoan DPSnaa SDPxon DSna SPDnaon SPxDSxa
Operation :
Objects :
D : destination P : pattern S : source
in HEX
FF FE FD FC FB FA F9 F8 F7 F6 F5 F4 F3 F2 F1 F0 EF EE ED EC EB EA E9 E8 E7 E6 E5 E4 E3 E2 E1 E0 DF DE DD DC DB
in R Polish
1 DPSoo PSDnoo PSo DPSnoo DPo PDSxno PDSao PDSano PDSxo PDno PSDnao PSno PDSnao PDSono P SDPnoo DSo SDPxno SDPao DPSxno DPSao DSPDSanaxxn SSPxDSxax SPxPDxan SDPSanax PDSPaoxn SDPSxax PSDPaoxn DSPDxax PDSoxn PDSoa SDPano SDPxo SDno SPDnao SPxDSxan
P121
25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52
PDSPanaxn SDPSaoxxn SDPSxnox DPSxa PSDPSaoxxn DPSana SSPxPDxaxn SPDSoax PSDnox PSDPxox PSDnoan PSna SDPnaon SDPSoox Sn SPDSaox SPDSxnox SDPox SDPoan PSDPoax SPDnox SPDSxox SPDnoan PSx SPDSonox SPDSnaox PSan PSDnaa DPSxon SDxPDxa SPDSanaxn SDna DPSnaon DSPDaox PSDPxaxn SDPxa PDSPDoaxxn DPSDoax PDSnox SDPana SSPxDSxoxn PDSPxox PDSnoan PDna DSPnaon DPSDaox
DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 CF CE CD CC CB CA C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 BF BE BD BC BB BA B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 AF AE AD
PDSPanax SDPSaoxn SDPSxax DPSxan PSDPSaoxx DPSanan SSPxPDxax SPDSoaxn PDSnax PSDPxoxn PSDnoa SPno SDPnao SDPono S SPDSaoxn DPSDxax SPDoxn SDPoa PSDPoaxn SDPnax SPDSxoxn SPDnoa PSxn SPDSonoxn SPDSnaoxn PSa DPSano DPSxo SDxPDxan SPDSanax DSno DPSnao DSPDaoxn PSDPxax SDPxan PDSPDoaxx DPSDoaxn PSDnax SDPanan SSPxDSxox PDSPxoxn PDSnoa DPno DSPnao DPSDaoxn
P122
53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F
SPDSxaxn DPSonon Dn DPSox DPSoan PDSPoax DPSnox DPx DPSDonox DPSDxox DPSnoan DPSDnaox DPan PDSxa DSPDSaoxxn DSPDoax SDPnox SDPSoax DSPnox DSx SDPSonox DSPDSonoxxn PDSxxn DPSax PSDPSoaxxn SDPax PDSPDoaxxn SDPSnoax PDSxnan PDSana SSDxPDxaxn SDPSxox SDPnoan DSPDxox DSPnoan SDPSnaox DSan PDSax DSPDSoaxxn DPSDnoax SDPxnan SPDSnoax DPSxnan SPxDSxo DPSaan
AC AB AA A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 9F 9E 9D 9C 9B 9A 99 98 97 96 95 94 93 92 91 90 8F 8E 8D 8C 8B 8A 89 88 87 86 85 84 83 82 81 80
SPDSxax DPSono D DPSoxn DPSoa PDSPoaxn DSPnax DPxn DPSDonoxn DPSDxoxn DPSnoa DPSDnaoxn DPa PDSxan DSPDSaoxx DSPDoaxn SPDnax SDPSoaxn DPSnax DSxn SDPSonoxn DSPDSonoxx PDSxx DPSaxn PSDPSoaxx SDPaxn PDSPDoaxx SDPSnoaxn PDSxna PDSanan SSDxPDxax SDPSxoxn SDPnoa DSPDxoxn DSPnoa SDPSnaoxn DSa PDSaxn DSPDSoaxx DPSDnoaxn SDPxna SPDSnoaxn DPSxna SPxDSxon DPSaa
P123
D. Memory Address Table
CPU Address Multiplexing - Symmetry Addressing
VGA Mode 16-bit / 32-bit CAS-A0 CAS-A1 CAS-A2 CAS-A3 CAS-A4 CAS-A5 CAS-A6 CAS-A7 CAS-A8 QA0/BANK0 PG CH SA2 SA3 SA4 SA5 SA6 0 Enhance 16 color Mode 16-bit / 32-bit//*
QA0/BANK0//BANK
Enhance 256/Hi-/Ture Color 16-bit / 32-bit QA0/BA3 BA0 BA1 SA2 SA3 SA4 SA5 SA6 BA2
Enhance Text Mode 16-bit / 32-bit QA0/BANK0 SA5 SA6 SA7 SA8 SA9 SA10 SA11 0
SA0 SA1 SA2 SA3 SA4 SA5 SA6
SA169/SA169//BAN
RAS-A0 RAS-A1 RAS-A2 RAS-A3 RAS-A4 RAS-A5 RAS-A6 RAS-A7 RAS-A8
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA159
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA159
SA0 SA1 SA2 SA3 SA4 SA12 SA13 SA14 SA159
* : Bank addressing for enhanced 16-color display mode [84.06.12 SP508T06.TBL]
P124
CPU Address Multiplexing - Asymmetry Addressing
VGA Mode 16-bit / 32-bit CAS-A0 CAS-A1 CAS-A2 CAS-A3 CAS-A4 CAS-A5 CAS-A6 CAS-A7 CAS-A8 QA0/BANK0 PG CH SA2 SA3 SA4 SA5 SA6 0 Enhance 16 color Mode 16-bit / 32-bit//*
QA0/BANK0//BANK
Enhance 256/Hi-/Ture Color 16-bit / 32-bit QA0/BA3 BA0 BA1 SA2 SA3 SA4 SA5 SA6 BA2
Enhance Text Mode 16-bit / 32-bit QA0/BANK0 SA5 SA6 SA7 SA8 SA9 SA10 SA11 0
SA0 SA1 SA2 SA3 SA4 SA5 SA6 0
RAS-A0 RAS-A1 RAS-A2 RAS-A3 RAS-A4 RAS-A5 RAS-A6 RAS-A7 RAS-A8 RAS-A9
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA159 0
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15
SA169/SA169//BAN
SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA159 BA2
SA0 SA1 SA2 SA3 SA4 SA12 SA13 SA14 SA159 0
* : Bank addressing for enhanced 16-color display mode [84.06.12 SP508T07.TBL]
P125
CRT Address Multiplexing - Symmetry Addressing
Byte Mode 16-bit / 32-bit CAS-A0 CAS-A1 CAS-A2 CAS-A3 CAS-A4 CAS-A5 CAS-A6 CAS-A7 CAS-A8 QA0/MA17 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA16 Word Mode 16-bit / 32-bit QA1/MA17 MA15/MA13 MA0 MA1 MA2 MA3 MA4 MA5 MA16 Double Word Mode 16-bit / 32-bit QA0/MA17 MA14 MA15 MA0 MA1 MA2 MA3 MA4 MA16 IBM Text Mode 16-bit / 32-bit QA1/MA17 RA0 RA1 RA2 RA3 RA4 ASC0 ASC1 0 Enhance Text Mode 16-bit / 32-bit QA1/ASC7 ASC0 ASC1 ASC2 ASC3 ASC4 ASC5 ASC6 0
RAS-A0 RAS-A1 RAS-A2 RAS-A3 RAS-A4 RAS-A5 RAS-A6 RAS-A7 RAS-A8
MA7 MA8 MA9 MA10 MA11 MA12 MA13/RA0 MA14/RA1 MA15
MA6 MA7 MA8 MA9 MA10 MA11 MA12/RA0 MA13/RA1 MA14
MA5 MA6 MA7 MA8 MA9 MA10 MA11/RA0 MA12/RA1 MA13
ASC2 ASC3 ASC4 ASC5 ASC6 ASC7 CHHAP2 CHHAP0 CHHAP1
RA0 RA1 RA2 RA3 RA4 0 CHHAP2 CHHAP0 CHHAP1
[84.06.13 SP508T08.TBL]
P126
CRT Address Multiplexing - Asymmetry Addressing
Byte Mode Word Mode 16-bit / 32-bit//* QA1/MA17 MA15/MA13 MA0 MA1 MA2 MA3 MA4 MA5 0 Double Word Mode 16-bit / 32-bit QA0/MA17 MA14 MA15 MA0 MA1 MA2 MA3 MA4 0 IBM Text Mode 16-bit / 32-bit QA1/MA17 RA0 RA1 RA2 RA3 RA4 ASC0 ASC1 0 Enhance Text Mode 16-bit / 32-bit QA1/ASC7 ASC0 ASC1 ASC2 ASC3 ASC4 ASC5 ASC6 0
16-bit / 32-bit CAS-A0 CAS-A1 CAS-A2 CAS-A3 CAS-A4 CAS-A5 CAS-A6 CAS-A7 CAS-A8 QA0/MA17 MA0 MA1 MA2 MA3 MA4 MA5 MA6 0
RAS-A0 RAS-A1 RAS-A2 RAS-A3 RAS-A4 RAS-A5 RAS-A6 RAS-A7 RAS-A8 RAS-A9
MA7 MA8 MA9 MA10 MA11 MA12 MA13/RA0 MA14/RA1 MA15 MA16
MA6 MA7 MA8 MA9 MA10 MA11 MA12/RA0 MA13/RA1 MA14 MA16
MA5 MA6 MA7 MA8 MA9 MA10 MA11/RA0 MA12/RA1 MA13 MA16
ASC2 ASC3 ASC4 ASC5 ASC6 ASC7 CHHAP2 CHHAP0 CHHAP1 0 [84.06.13
RA0 RA1 RA2 RA3 RA4 0 CHHAP2 CHHAP0 CHHAP1 0 SP508T09.TBL]
P127
BA0 to BA4 Selection Table
Bank Addressing mode BA0 BA1 BA2 BA3 BA4 BANK0 BANK1 BANK2 BANK3 BANK4 [84.06.26 Linear Addressing mode SA16 SA17 SA18 SA19 SA20 SP508T10.TBL]
PG*,CH*,SAA* Table
EXTMEM ODD/EVEN EGA/128K X 0 1 1 X 0 1 1 1 X Byte mode Word Mode Dword Mode EXTMEM : Sequencer Register indexed hex 04 bit 1 ODD/EVEN : Graphics Control Register indexed hex 06 bit 1 VGA CHAIN4 : Sequencer Register indexed hex 04 bit 3 EGA128K : 1- Graphics Control Register indexed hex 06 bit 2=0 and bit 3=0 0- Graphics Control Register indexed hex 06 bit 2=1 and bit 3=1 PAGBIT : Miscellaneousn Output Register bit 5 ** : 256K 64-bit bus--BA2 , 512k 64-bit bus--BA3 [84.09.08 SP508T11.TBL]
P128
VGA CHAIN4 0 0 0 0 1 0 1
PG* SA0 SA14 SA16 /PAGBIT 0 BA2/BA3** -
CH* SA1 0 BA2/BA3** -
SAA* SA2 BA2/BA3**
X 0 1 0 X -
-
E. MCLK & VCLK Frequency Programming Table
TP6508 VGA VCLK Synthesizer Parameter Table
VCLK SPEC. 25.175 25.267 28.322 28.636 31.5 32.514 34 35 36 40 44.9 49.5 50 56.644 57.272 58.8 65 70 75 78.75 85 90 94.5 100 102.4 108 110 115 120 129.4 135 VCLK Frequenc 25.165 25.2671 28.2991 28.636 31.4996 32.5188 33.8425 34.9996 35.9995 39.9823 44.9065 49.5325 50.3299 56.5982 57.272 58.7993 65.0115 69.9991 75.0461 78.749 84.8853 89.9989 94.4988 99.9214 102.3954 107.9986 110.023 114.544 119.7985 129.3923 134.998 O 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 1C E 29 14 A 42 0C 0A E F A 12 39 53 47 4C 18 2B 10 A 52 4C 41 51 18 10 48 11 2B 2A 20 D 41 10 54 29 9 3A A 8 B 16 6 A 20 54 47 4A 15 23 C 3 37 30 27 2E 6 8 25 8 14 12 6 P 1 0 1 1 1 0 0 0 0 1 0 0 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 REG. 22/C3h 23/C4h 9C 8E A9 94 8A C2 8C 8A 8E 8F 8A 92 B9 53 47 4C 18 2B 10 0A 52 4C 41 51 18 10 48 11 2B 2A 20 REG. 24/C5h 25/C6h 83 20 A9 53 12 74 14 10 16 2D 0C 14 40 A9 8F 95 2B 47 19 06 6F 61 4F 5D 0C 11 4B 11 29 25 0C
[88.04.12 TPVGAV2.TBL]
HM8694-304 00,00 00,01 00,01 10,10 00,10 0 1 1 A 2
00,11 01,00 01,01 01,10 11,00 10,11 01,11 11,01 11,10
3 4 5 6 C B 7 D E
P129
TP6508 VGA MCLK Synthesizer Parameter Table
MCLK SPEC. 30MHz 33MHz 36MHz 40MHz 45MHz 50MHz 55MHz 60MHz 65MHz 68MHz 69MHz 70MHz 71MHz 72MHz 73MHz 74MHz 75MHz 78MHz 80MHz 82MHz 85MHz 88MHz 90MHz 95MHz 100MHz MCLK Frequenc 29.9996 33.0042 36.0259 39.9823 44.9994 49.9294 54.9993 59.9992 64.9817 68.0105 69.9867 69.9991 70.9675 72.0519 72.9937 74.0345 74.9743 77.9874 80.034 82.0383 85.0898 88.0033 89.9989 94.9877 99.893 O 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 24 21 26 24 20 21 78 41 3A 38 34 41 38 4D 40 34 47 3F 6C 34 33 3E 36 43 4A D 3E 3A 3D 34 29 26 3E 3E 33 2F 2B 35 2D 3D 32 28 36 2E 26 34 22 28 22 28 2A P 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 REG. 26/C9h A0 A1 A6 A4 A0 A1 78 41 3A 38 34 41 38 4D 40 34 47 3F 6C 34 33 3E 36 43 4A
[88.04.12
REG. 27/CAh 7D 75 7B 69 53 4D 7C 7D 67 5F 57 6B 5B 7B 65 51 6D 5D 4C 49 45 51 45 51 55
TPVGAM2.TBL]
P130
F. Pins Selection Configuration
*1. Disable internal dual frequency synthesizer
( SREG D0 D4 = 0 ) PIN Name PIN Number OFF 178 XTAL1 203 Selected Multipelx Function EXVCLK ~ External VCLK input EXMCLK ~ External MCLK input
*2. VGA BIOS ROM interface
( SREG D0 D2-0 = 101 ) ~ ISA Bus PIN Name PIN Number ROMCS* 29 Selected Multipelx Function BIOS ROM chip_select signal output
*3. OFF pin control selection (Pin Number =178 )
( if SREG CE D0 = 1 & if *1 isn't true ) ~ SREG CB D1-0 = selection bits D1 D0 Selected Multipelx Function 0 0 VESA DPMS OFF mode pin trigger input/output pin 0 1 Output internal MCLK frequency signal 1 x Output internal VCLK frequency signal
*4. 24-bit TFT panel interface selection
( CREG AC D5 = 1 ) PIN Name PIN Number CA[7:0] 97-90 Selected Multipelx Function P[23:16] ~ Flat panel data signals
*5. Video interface selection
[a]. ( SREG D9 D1-0 = 01 ) ~ 18-bit video port interface PIN Name : RASC* , WEC*, CASCH*, CASCL* , MCD[15:0] Selected Multipelx Function : KEY , PCLK , VR[7:2] ,VG[7:2] , VB[7:2] [b]. ( SREG D9 D1-0 = 11 , SREG D0 D6 = 1 ) ~ 24-bit video port interface PIN Name : RASC* , CASCH*, CASCL* , WEC*, MCD[15:0] , OEC* , 32KHZ , CA8 , CA9 , A27 , A26 Selected Multipelx Function : KEY , PCLK , VR[7:2] ,VG[7:2] , VB[7:2] , VR[1,0] , VG[1,0] , VB[1:0] [c]. ( SREG D9 D0 = 0 , SREG D0 D6 = 1 , SREG C0 D6=1) ~ VAFC interface PIN Name : RASC* , CASCH*, CASCL* , WEC*, MCD[15:0] , OEC* , 32KHZ , CA8 , CA9 , A27 , A26 Selected Multipelx Function : VRDY , PCLK , GRDY , EVID# , VP[15:0] , VCLK , BLANK*
*6. External LCD frame buffer interface selection
( if *4,*5 isn't true) PIN Name : RASC* , CASCH*, CASCL* , WEC*, MCD[15:0] , OEC* , CA[9:0] Selected Multipelx Function : External LCD frame buffer DRAM interface
*7. ACTI & FPBACK output selection
( CREG D0 D6 = 1 , & if *5 [b] ) PIN Name PIN Number A26 53 A27 54 Selected Multipelx Function ACTI ~ responses high during valid VGA access FPBACK ~ Flat panel power control signal output
*8. Pin-61 output control
( SREG D1 D4 = selection bit ) D7 Selected Multipelx Function 0 FPVEE ~ Flat panel power control signal output 1 FPBACK ~ Flat panel power control signal output P131

▲Up To Search▲

Price & Availability of TP6508

	To Download TP6508 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .